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I2C Registers
Table 21-27. I2C_CON Register Field Descriptions (continued)
Bit Field Type Reset Description
3-2 Reserved R 0h
1 STP R/W 0h Stop condition (I2C master mode only).
This bit can be set to a 1 by the CPU to generate a stop condition.
It is reset to 0 by the hardware after the stop condition has been
generated.
The stop condition is generated when DCOUNT passes 0.
When this bit is not set to 1 before the end of the transfer (DCOUNT
= 0), the stop condition is not generated and the SCL line is hold to 0
by the master, which can re-start a new transfer by setting the STT
bit to 1.
Value after reset is low
0x0 = No action or stop condition detected
0x1 = Stop condition queried
0 STT R/W 0h Start condition (I2C master mode only).
This bit can be set to a 1 by the CPU to generate a start condition.
It is reset to 0 by the hardware after the start condition has been
generated.
The start/stop bits can be configured to generate different transfer
formats.
Value after reset is low.
Note: DCOUNT is data count value in I2C_CNT register.
STT = 1, STP = 0, Conditions = Start, Bus Activities = S-A-D.
STT = 0, STP = 1, Conditions = Stop, Bus Activities = P.
STT = 1, STP = 1, Conditions = Start-Stop (DCOUNT=n), Bus
Activities = S-A-D..(n)..D-P.
STT = 1, STP = 0, Conditions = Start (DCOUNT=n), Bus Activities =
S-A-D..(n)..D.
0x0 = No action or start condition detected
0x1 = Start condition queried
3751
SPRUH73H–October 2011–Revised April 2013 I2C
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