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Table 7-113. SDRAM_CONFIG Register Field Descriptions (continued)
Bit Field Type Reset Description
15-14 reg_narrow_mode R/W 0h SDRAM data bus width.
Set to 0 for
32-bit and set to 1 for
16-bit.
All other values are reserved.
13-10 reg_cl R/W 0h CAS Latency.
The value of this field defines the CAS latency to be used when
accessing connected SDRAM devices.
Value of 2, 3, 5, and 6 (CAS latency of 2, 3, 1.5, and 2.5) are
supported for DDR1.
Value of 2, 3, 4, and 5 (CAS latency of 2, 3, 4, and 5) are supported
for DDR2.
Value of 2, 4, 6, 8, 10, 12, and 14 (CAS latency of 5, 6, 7, 8, 9, 10,
and 11) are supported for DDR3.
Value of 2 and 3 (CAS latency of 2 and 3) are supported for
LPDDR1.
All other values are reserved.
9-7 reg_rowsize R/W 0h Row Size.
Defines the number of row address bits of connected SDRAM
devices.
Set to 0 for 9 row bits, set to 1 for 10 row bits, set to 2 for 11 row
bits, set to 3 for 12 row bits, set to 4 for 13 row bits, set to 5 for 14
row bits, set to 6 for 15 row bits, and set to 7 for 16 row bits.
This field is only used when reg_ibank_pos field in SDRAM Config
register is set to 1, 2, or 3, or reg_ebank_pos field in SDRAM
Config_2 register is set to 1.
6-4 reg_ibank R/W 0h Internal Bank setup.
Defines number of banks inside connected SDRAM devices.
Set to 0 for 1 bank, set to 1 for 2 banks, set to 2 for 4 banks, and set
to 3 for 8 banks.
All other values are reserved.
3 reg_ebank R/W 0h External chip select setup.
Defines whether SDRAM accesses will use 1 or 2 chip select lines.
Set to 0 to use pad_cs_o_n[0] only.
All other values reserved.
2-0 reg_pagesize R/W 0h Page Size.
Defines the internal page size of connected SDRAM devices.
Set to 0 for
256-word page (8 column bits), set to 1 for
512-word page (9 column bits), set to 2 for
1024-word page (10 column bits), and set to 3 for
2048-word page (11 column bits).
All other values are reserved.
427
SPRUH73H–October 2011–Revised April 2013 Memory Subsystem
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