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Table 17-14. MAILBOX REGISTERS (continued)
Offset Acronym Register Name Section
12Ch IRQENABLE_CLR_2 The interrupt enable register enables to mask the Section 17.1.5.38
module internal source of interrupt to the corresponding
user.
This register is write 1 to clear.
130h IRQSTATUS_RAW_3 The interrupt status register has the status for each Section 17.1.5.39
event that may be responsible for the generation of an
interrupt to the corresponding user - write 1 to a given bit
resets this bit.
This register is mainly used for debug purpose.
134h IRQSTATUS_CLR_3 The interrupt status register has the status combined Section 17.1.5.40
with irq-enable for each event that may be responsible
for the generation of an interrupt to the corresponding
user - write 1 to a given bit resets this bit.
138h IRQENABLE_SET_3 The interrupt enable register enables to unmask the Section 17.1.5.41
module internal source of interrupt to the corresponding
user.
This register is write 1 to set.
13Ch IRQENABLE_CLR_3 The interrupt enable register enables to mask the Section 17.1.5.42
module internal source of interrupt to the corresponding
user.
This register is write 1 to clear.
3247
SPRUH73H–October 2011–Revised April 2013 Interprocessor Communication
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