Texas Instruments AM335 Series Technical Reference Manual

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Table 17-14. MAILBOX REGISTERS (continued)
Offset Acronym Register Name Section
C8h MSGSTATUS_2 The message status register has the status of the Section 17.1.5.21
messages in the mailbox
CCh MSGSTATUS_3 The message status register has the status of the Section 17.1.5.22
messages in the mailbox
D0h MSGSTATUS_4 The message status register has the status of the Section 17.1.5.23
messages in the mailbox
D4h MSGSTATUS_5 The message status register has the status of the Section 17.1.5.24
messages in the mailbox
D8h MSGSTATUS_6 The message status register has the status of the Section 17.1.5.25
messages in the mailbox
DCh MSGSTATUS_7 The message status register has the status of the Section 17.1.5.26
messages in the mailbox
100h IRQSTATUS_RAW_0 The interrupt status register has the status for each Section 17.1.5.27
event that may be responsible for the generation of an
interrupt to the corresponding user - write 1 to a given bit
resets this bit.
This register is mainly used for debug purpose.
104h IRQSTATUS_CLR_0 The interrupt status register has the status combined Section 17.1.5.28
with irq-enable for each event that may be responsible
for the generation of an interrupt to the corresponding
user - write 1 to a given bit resets this bit.
108h IRQENABLE_SET_0 The interrupt enable register enables to unmask the Section 17.1.5.29
module internal source of interrupt to the corresponding
user.
This register is write 1 to set.
10Ch IRQENABLE_CLR_0 The interrupt enable register enables to mask the Section 17.1.5.30
module internal source of interrupt to the corresponding
user.
This register is write 1 to clear.
110h IRQSTATUS_RAW_1 The interrupt status register has the status for each Section 17.1.5.31
event that may be responsible for the generation of an
interrupt to the corresponding user - write 1 to a given bit
resets this bit.
This register is mainly used for debug purpose.
114h IRQSTATUS_CLR_1 The interrupt status register has the status combined Section 17.1.5.32
with irq-enable for each event that may be responsible
for the generation of an interrupt to the corresponding
user - write 1 to a given bit resets this bit.
118h IRQENABLE_SET_1 The interrupt enable register enables to unmask the Section 17.1.5.33
module internal source of interrupt to the corresponding
user.
This register is write 1 to set.
11Ch IRQENABLE_CLR_1 The interrupt enable register enables to mask the Section 17.1.5.34
module internal source of interrupt to the corresponding
user.
This register is write 1 to clear.
120h IRQSTATUS_RAW_2 The interrupt status register has the status for each Section 17.1.5.35
event that may be responsible for the generation of an
interrupt to the corresponding user - write 1 to a given bit
resets this bit.
This register is mainly used for debug purpose.
124h IRQSTATUS_CLR_2 The interrupt status register has the status combined Section 17.1.5.36
with irq-enable for each event that may be responsible
for the generation of an interrupt to the corresponding
user - write 1 to a given bit resets this bit.
128h IRQENABLE_SET_2 The interrupt enable register enables to unmask the Section 17.1.5.37
module internal source of interrupt to the corresponding
user.
This register is write 1 to set.
3246
Interprocessor Communication SPRUH73H–October 2011–Revised April 2013
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Texas Instruments AM335 Series Specifications

General

Brand	Texas Instruments
Model	AM335 Series
Category	Computer Hardware
Language	English