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5.3.2 SGX Elements Description .................................................................................... 184
6 Interrupts ........................................................................................................................ 186
6.1 Functional Description ................................................................................................... 187
6.1.1 Interrupt Processing ............................................................................................ 188
6.1.2 Register Protection ............................................................................................. 189
6.1.3 Module Power Saving .......................................................................................... 189
6.1.4 Error Handling ................................................................................................... 189
6.1.5 Interrupt Handling ............................................................................................... 189
6.2 Basic Programming Model .............................................................................................. 190
6.2.1 Initialization Sequence ......................................................................................... 190
6.2.2 INTC Processing Sequence ................................................................................... 190
6.2.3 INTC Preemptive Processing Sequence ..................................................................... 194
6.2.4 Interrupt Preemption ............................................................................................ 198
6.2.5 ARM A8 INTC Spurious Interrupt Handling ................................................................. 198
6.3 ARM Cortex-A8 Interrupts .............................................................................................. 199
6.4 PWM Events .............................................................................................................. 203
6.5 Interrupt Controller Registers ........................................................................................... 204
6.5.1 INTC Registers .................................................................................................. 204
7 Memory Subsystem ......................................................................................................... 250
7.1 GPMC ..................................................................................................................... 251
7.1.1 Introduction ...................................................................................................... 251
7.1.2 Integration ........................................................................................................ 254
7.1.3 Functional Description .......................................................................................... 256
7.1.4 Use Cases ....................................................................................................... 355
7.1.5 Registers ......................................................................................................... 366
7.2 OCMC-RAM .............................................................................................................. 398
7.2.1 Introduction ...................................................................................................... 398
7.2.2 Integration ........................................................................................................ 399
7.3 EMIF ....................................................................................................................... 400
7.3.1 Introduction ...................................................................................................... 400
7.3.2 Integration ........................................................................................................ 402
7.3.3 Functional Description .......................................................................................... 404
7.3.4 Use Cases ....................................................................................................... 422
7.3.5 EMIF4D Registers .............................................................................................. 422
7.3.6 DDR2/3/mDDR PHY Registers ............................................................................... 467
7.4 ELM ........................................................................................................................ 476
7.4.1 Introduction ...................................................................................................... 476
7.4.2 Integration ........................................................................................................ 477
7.4.3 Functional Description .......................................................................................... 478
7.4.4 Basic Programming Model ..................................................................................... 481
7.4.5 ELM Registers ................................................................................................... 487
8 Power, Reset, and Clock Management (PRCM) .................................................................... 499
8.1 Power, Reset, and Clock Management ............................................................................... 500
8.1.1 Introduction ...................................................................................................... 500
8.1.2 Device Power-Management Architecture Building Blocks ................................................. 500
8.1.3 Clock Management ............................................................................................. 500
8.1.4 Power Management ............................................................................................ 506
8.1.5 PRCM Module Overview ....................................................................................... 517
8.1.6 Clock Generation and Management .......................................................................... 519
8.1.7 Reset Management ............................................................................................. 535
8.1.8 Power-Up/Down Sequence .................................................................................... 544
8.1.9 IO State ........................................................................................................... 544
8.1.10 Voltage and Power Domains ................................................................................. 544
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SPRUH73H–October 2011–Revised April 2013 Contents
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