Texas Instruments AM335 Series Technical Reference Manual

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Table 22-10. McASP Registers Accessed Through Configuration Bus (continued)
Offset Acronym Register Description Section
100h DITCSRA0 Left (even TDM time slot) channel status register (DIT mode) 0 Section 22.4.1.38
104h DITCSRA1 Left (even TDM time slot) channel status register (DIT mode) 1 Section 22.4.1.38
108h DITCSRA2 Left (even TDM time slot) channel status register (DIT mode) 2 Section 22.4.1.38
10Ch DITCSRA3 Left (even TDM time slot) channel status register (DIT mode) 3 Section 22.4.1.38
110h DITCSRA4 Left (even TDM time slot) channel status register (DIT mode) 4 Section 22.4.1.38
114h DITCSRA5 Left (even TDM time slot) channel status register (DIT mode) 5 Section 22.4.1.38
118h DITCSRB0 Right (odd TDM time slot) channel status register (DIT mode) 0 Section 22.4.1.39
11Ch DITCSRB1 Right (odd TDM time slot) channel status register (DIT mode) 1 Section 22.4.1.39
120h DITCSRB2 Right (odd TDM time slot) channel status register (DIT mode) 2 Section 22.4.1.39
124h DITCSRB3 Right (odd TDM time slot) channel status register (DIT mode) 3 Section 22.4.1.39
128h DITCSRB4 Right (odd TDM time slot) channel status register (DIT mode) 4 Section 22.4.1.39
12Ch DITCSRB5 Right (odd TDM time slot) channel status register (DIT mode) 5 Section 22.4.1.39
130h DITUDRA0 Left (even TDM time slot) channel user data register (DIT mode) 0 Section 22.4.1.40
134h DITUDRA1 Left (even TDM time slot) channel user data register (DIT mode) 1 Section 22.4.1.40
138h DITUDRA2 Left (even TDM time slot) channel user data register (DIT mode) 2 Section 22.4.1.40
13Ch DITUDRA3 Left (even TDM time slot) channel user data register (DIT mode) 3 Section 22.4.1.40
140h DITUDRA4 Left (even TDM time slot) channel user data register (DIT mode) 4 Section 22.4.1.40
144h DITUDRA5 Left (even TDM time slot) channel user data register (DIT mode) 5 Section 22.4.1.40
148h DITUDRB0 Right (odd TDM time slot) channel user data register (DIT mode) 0 Section 22.4.1.41
14Ch DITUDRB1 Right (odd TDM time slot) channel user data register (DIT mode) 1 Section 22.4.1.41
150h DITUDRB2 Right (odd TDM time slot) channel user data register (DIT mode) 2 Section 22.4.1.41
154h DITUDRB3 Right (odd TDM time slot) channel user data register (DIT mode) 3 Section 22.4.1.41
158h DITUDRB4 Right (odd TDM time slot) channel user data register (DIT mode) 4 Section 22.4.1.41
15Ch DITUDRB5 Right (odd TDM time slot) channel user data register (DIT mode) 5 Section 22.4.1.41
180h SRCTL0 Serializer control register 0 Section 22.4.1.37
184h SRCTL1 Serializer control register 1 Section 22.4.1.37
188h SRCTL2 Serializer control register 2 Section 22.4.1.37
18Ch SRCTL3 Serializer control register 3 Section 22.4.1.37
200h XBUF0 Transmit buffer register for serializer 0 Section 22.4.1.42
204h XBUF1 Transmit buffer register for serializer 1 Section 22.4.1.42
208h XBUF2 Transmit buffer register for serializer 2 Section 22.4.1.42
20Ch XBUF3 Transmit buffer register for serializer 3 Section 22.4.1.42
280h RBUF0 Receive buffer register for serializer 0 Section 22.4.1.43
284h RBUF1 Receive buffer register for serializer 1 Section 22.4.1.43
288h RBUF2 Receive buffer register for serializer 2 Section 22.4.1.43
28Ch RBUF3 Receive buffer register for serializer 3 Section 22.4.1.43
Table 22-11. McASP AFIFO Registers Accessed Through Peripheral Configuration Port
Offset Acronym Register Description Section
1000h WFIFOCTL Write FIFO control register Section
22.4.1.44
1004h WFIFOSTS Write FIFO status register Section
22.4.1.45
1008h RFIFOCTL Read FIFO control register Section
22.4.1.46
3827
SPRUH73H–October 2011–Revised April 2013 Multichannel Audio Serial Port (McASP)
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Texas Instruments AM335 Series Specifications

General

Brand	Texas Instruments
Model	AM335 Series
Category	Computer Hardware
Language	English