EDMA3 Registers
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Table 11-100. Source Active Options Register (SAOPT) Field Descriptions (continued)
Bit Field Value Description
6-4 PRI 0-7h Transfer priority. Reflects the values programmed in the QUEPRI register in the EDMACC.
0 Priority 0 - Highest priority
1h-6h Priority 1 to priority 6
7h Priority 7 - Lowest priority
3-2 Reserved 0 Reserved. Always write 0 to this bit; writes of 1 to this bit are not supported and attempts to do so may
result in undefined behavior.
1 DAM Destination address mode within an array
0 Increment (INCR) mode. Destination addressing within an array increments.
1 Constant addressing (CONST) mode. Destination addressing within an array wraps around upon
reaching FIFO width.
0 SAM Source address mode within an array
0 Increment (INCR) mode. Source addressing within an array increments.
1 Constant addressing (CONST) mode. Source addressing within an array wraps around upon reaching
FIFO width.
1006
Enhanced Direct Memory Access (EDMA) SPRUH73H–October 2011–Revised April 2013
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