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Appendix A
Step 4. Initiate transfer
(a) This step is highly dependent on the event trigger source:
(i) If the source is an external event coming from a peripheral, the peripheral will be
enabled to start generating relevant EDMA3 events that can be latched to the ER
transfer.
(ii) For QDMA events, writes to the trigger word (step 2-a above) will initiate the transfer.
(iii) Manually triggered transfers will be initiated by writes to the Event Set Registers
(ESR/ESRH).
(iv) Chained-trigger events initiate when a previous transfer returns a transfer completion
code equal to the chained channel number.
Step 5. Wait for completion
(a) If the interrupts are enabled as mentioned in step 3 above, then the EDMA3CC will
generate a completion interrupt to the CPU whenever transfer completion results in setting
the corresponding bits in the interrupt pending register (IPR/IPRH). The set bits must be
cleared in the IPR\IPRH by writing to corresponding bit in ICR\ICRH.
(b) If polling for completion (interrupts not enabled in the device controller), then the
application code can wait on the expected bits to be set in the IPR\IPRH. Again, the set
bits in the IPR\IPRH must be manually cleared via ICR\ICRH before the next set of
transfers is performed for the same transfer completion code values.
1021
SPRUH73H–October 2011–Revised April 2013 Enhanced Direct Memory Access (EDMA)
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