MCLK + LCD_CLK when CLKDIV + 0.
MCLK +
LCD_CLK
CLKDIV
when CLKDIV 0 0.
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Functional Description
Table 13-6. LIDD I/O Name Map
Interface Data LIDD_CTRL Display I/O
Display Type Type Bits [2:0] I/O Name Name Comment
Character HD44780 4 100 LCD_DATA[7:4] DATA[7:4] Data Bus (length defined by
Display Type Instruction)
LCD_AC_BIAS_EN E (or E0) Enable Strobe (first display)
LCD_HSYNC R/W Read/Write
LCD_VSYNC RS Register Select (Data/not
Instruction)
LCD_MCLK E1 Enable Strobe (second display
optional)
Character HD44780 8 100 LCD_DATA[7:0] DATA[7:0] Data Bus (length defined by
Display Type Instruction)
LCD_AC_BIAS_EN E (or E0) Enable Strobe (first display)
LCD_HSYNC R/W Read/Write
LCD_VSYNC RS Register Select (Data/not
Instruction)
LCD_MCLK E1 Enable Strobe (second display
optional)
Micro Interface 6800 Up to 001 LCD_DATA[15:0] DATA[7:0] Data Bus (16 bits always
Graphic Display Family 16 available)
LCD_PCLK E Enable Clock
LCD_HSYNC R/W Read/Write
LCD_VSYNC A0 Address/Data Select
LCD_AC_BIAS_EN CS (or CS0) Chip Select (first display)
LCD_MCLK CS1 Chip Select (second display
optional)
000 LCD_MCLK None Synchronous Clock (optional)
Micro Interface 8080 Up to 011 LCD_DATA[15:0] DATA[7:0] Data Bus (16 bits always
Graphic Display Family 16 available)
LCD_PCLK RD Read Strobe
LCD_HSYNC WR Write Strobe
LCD_VSYNC A0 Address/Data Select
LCD_AC_BIAS_EN CS (or CS0) Chip Select (first display)
LCD_MCLK CS1 Chip Select (second display
optional)
010 LCD_MCLK None Synchronous Clock (optional)
The timing parameters are defined by the LIDD_CS0_CONF and LIDD_CS1_CONF registers, which are
described in Section 13.5.4 and Section 13.5.7.
The timing configuration is based on an internal reference clock, MCLK. The MCLK is generated out of
LCD_CLK, which is determined by the CLKDIV bit in the LCD_CTRL register.
See your device-specific data manual for the timing configurations supported by the LCD controller.
1107
SPRUH73H–October 2011–Revised April 2013 LCD Controller
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