1 BPP Example 2 BPP Example
Palette
RAM
Palette
RAM
256
entries
256
entries
12 bits 12 bits
4 BPP Example 8 BPP Example
Palette
RAM
Palette
RAM
256
entries
256
entries
12 bits 12 bits
1 bpp data value used
to select contents
from one of these 2
locations
2 bpp data value used
to select contents
from one of these 4
locations
4 bpp data value used
to select contents
from one of these 16
locations
8 bpp data value used
to select contents
from one of these 256
locations
Programming Model
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Figure 13-18. Palette Lookup Examples
A 16-bit halfword is read from the DDR frame buffer. This halfword can be byte lane and halfword
swapped using the DMA configuration values cfg_byte_swap and cfg_bigendian. This section will deal
with the frame buffer data as it is returned post swapped from the DMA module.
The DMA module actually outputs a 32-bit word. The Palette Lookup logic uses the lower halfword first,
followed by the upper halfword. The cfg_rdorder and cfg_nibmode registers determine the raster read
ordering of the frame buffer data to be sent to the palette lookup table.
There are precedence rules for the hardware as it parses each 16-bit word from the frame buffer.
1. If cfg_rdorder = ‘0’, the data halfword is parsed from the least significant bit to the most significant bit.
2. Else, if cfg_nibmode = ‘1’, the data halfword is parsed byte swapped with the scan order going from
the most significant bit of each byte to the least significant bit of each byte.
3. Otherwise, the data halfword is parsed from the most significant bit to the least significant bit.
The bitwise scan order for each halfword fetched from the frame buffer is shown in the following lists. The
bitfields returned are used to determine the addressing of the Palette RAM.
1126
LCD Controller SPRUH73H–October 2011–Revised April 2013
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