Ethernet Subsystem Registers
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Table 14-39. CPSW_CPDMA REGISTERS
Offset Acronym Register Name Section
0h TX_IDVER CPDMA_REGS TX IDENTIFICATION AND VERSION Section 14.5.2.1
REGISTER
4h TX_CONTROL CPDMA_REGS TX CONTROL REGISTER Section 14.5.2.2
8h TX_TEARDOWN CPDMA_REGS TX TEARDOWN REGISTER Section 14.5.2.3
10h RX_IDVER CPDMA_REGS RX IDENTIFICATION AND VERSION Section 14.5.2.4
REGISTER
14h RX_CONTROL CPDMA_REGS RX CONTROL REGISTER Section 14.5.2.5
18h RX_TEARDOWN CPDMA_REGS RX TEARDOWN REGISTER Section 14.5.2.6
1Ch CPDMA_SOFT_RESET CPDMA_REGS SOFT RESET REGISTER Section 14.5.2.7
20h DMACONTROL CPDMA_REGS CPDMA CONTROL REGISTER Section 14.5.2.8
24h DMASTATUS CPDMA_REGS CPDMA STATUS REGISTER Section 14.5.2.9
28h RX_BUFFER_OFFSET CPDMA_REGS RECEIVE BUFFER OFFSET Section 14.5.2.10
2Ch EMCONTROL CPDMA_REGS EMULATION CONTROL Section 14.5.2.11
30h TX_PRI0_RATE CPDMA_REGS TRANSMIT (INGRESS) PRIORITY 0 Section 14.5.2.12
RATE
34h TX_PRI1_RATE CPDMA_REGS TRANSMIT (INGRESS) PRIORITY 1 Section 14.5.2.13
RATE
38h TX_PRI2_RATE CPDMA_REGS TRANSMIT (INGRESS) PRIORITY 2 Section 14.5.2.14
RATE
3Ch TX_PRI3_RATE CPDMA_REGS TRANSMIT (INGRESS) PRIORITY 3 Section 14.5.2.15
RATE
40h TX_PRI4_RATE CPDMA_REGS TRANSMIT (INGRESS) PRIORITY 4 Section 14.5.2.16
RATE
44h TX_PRI5_RATE CPDMA_REGS TRANSMIT (INGRESS) PRIORITY 5 Section 14.5.2.17
RATE
48h TX_PRI6_RATE CPDMA_REGS TRANSMIT (INGRESS) PRIORITY 6 Section 14.5.2.18
RATE
4Ch TX_PRI7_RATE CPDMA_REGS TRANSMIT (INGRESS) PRIORITY 7 Section 14.5.2.19
RATE
80h TX_INTSTAT_RAW CPDMA_INT TX INTERRUPT STATUS REGISTER Section 14.5.2.20
(RAW VALUE)
84h TX_INTSTAT_MASKED CPDMA_INT TX INTERRUPT STATUS REGISTER Section 14.5.2.21
(MASKED VALUE)
88h TX_INTMASK_SET CPDMA_INT TX INTERRUPT MASK SET REGISTER Section 14.5.2.22
8Ch TX_INTMASK_CLEAR CPDMA_INT TX INTERRUPT MASK CLEAR Section 14.5.2.23
REGISTER
90h CPDMA_IN_VECTOR CPDMA_INT INPUT VECTOR (READ ONLY) Section 14.5.2.24
94h CPDMA_EOI_VECTOR CPDMA_INT END OF INTERRUPT VECTOR Section 14.5.2.25
A0h RX_INTSTAT_RAW CPDMA_INT RX INTERRUPT STATUS REGISTER Section 14.5.2.26
(RAW VALUE)
A4h RX_INTSTAT_MASKED CPDMA_INT RX INTERRUPT STATUS REGISTER Section 14.5.2.27
(MASKED VALUE)
A8h RX_INTMASK_SET CPDMA_INT RX INTERRUPT MASK SET REGISTER Section 14.5.2.28
ACh RX_INTMASK_CLEAR CPDMA_INT RX INTERRUPT MASK CLEAR Section 14.5.2.29
REGISTER
B0h DMA_INTSTAT_RAW CPDMA_INT DMA INTERRUPT STATUS REGISTER Section 14.5.2.30
(RAW VALUE)
B4h DMA_INTSTAT_MASKED CPDMA_INT DMA INTERRUPT STATUS REGISTER Section 14.5.2.31
(MASKED VALUE)
B8h DMA_INTMASK_SET CPDMA_INT DMA INTERRUPT MASK SET REGISTER Section 14.5.2.32
BCh DMA_INTMASK_CLEAR CPDMA_INT DMA INTERRUPT MASK CLEAR Section 14.5.2.33
REGISTER
C0h RX0_PENDTHRESH CPDMA_INT RECEIVE THRESHOLD PENDING Section 14.5.2.34
REGISTER CHANNEL 0
1256
Ethernet Subsystem SPRUH73H–October 2011–Revised April 2013
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