PRD
4
4 4
PRD
4
1
2
3
0
1
2
3
0
1
2
3
0
Z
1
2
3
4
0
1
2
3
CTR_dir
1
2
3
4
0
1
2
3
0
Up Down Down
Up
T
PWM =
(TBPRD + 1) x T
TBCLK
For Up Count and Down Count
For Up and Down Count
F
PW
M
=
1/ (T
PWM)
T
PWM =
2 x TBPRD x T
TBCLK
F
PWM =
1 / (T
PWM)
1
2
3
4
0
1
2
3
4
0
1
2
3
0
T
PWM
Z
T
PWM
T
PWM
T
PWM
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Enhanced PWM (ePWM) Module
Figure 15-11. Time-Base Frequency and Period
15.2.2.3.3.1 Time-Base Period Shadow Register
The time-base period register (TBPRD) has a shadow register. Shadowing allows the register update to
be synchronized with the hardware. The following definitions are used to describe all shadow registers in
the ePWM module:
• Active Register: The active register controls the hardware and is responsible for actions that the
hardware causes or invokes.
• Shadow Register: The shadow register buffers or provides a temporary holding location for the active
register. It has no direct effect on any control hardware. At a strategic point in time the shadow
register's content is transferred to the active register. This prevents corruption or spurious operation
due to the register being asynchronously modified by software.
The memory address of the shadow period register is the same as the active register. Which register is
written to or read from is determined by the TBCTL[PRDLD] bit. This bit enables and disables the TBPRD
shadow register as follows:
• Time-Base Period Shadow Mode: The TBPRD shadow register is enabled when TBCTL[PRDLD] =
0. Reads from and writes to the TBPRD memory address go to the shadow register. The shadow
register contents are transferred to the active register (TBPRD (Active) ← TBPRD (shadow)) when the
time-base counter equals zero (TBCNT = 0000h). By default the TBPRD shadow register is enabled.
• Time-Base Period Immediate Load Mode: If immediate load mode is selected (TBCTL[PRDLD] = 1),
then a read from or a write to the TBPRD memory address goes directly to the active register.
1505
SPRUH73H–October 2011–Revised April 2013 Pulse-Width Modulation Subsystem (PWMSS)
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