Enhanced PWM (ePWM) Module
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Table 15-53. EPWM1 Initialization for Figure 15-66
Register Bit Value Comments
TBPRD TBPRD 450 (1C2h) Period = 900 TBCLK counts
TBPHS TBPHS 0 Clear Phase Register to 0
TBCTL CTRMODE TB_UPDOWN
PHSEN TB_DISABLE Phase loading disabled
PRDLD TB_SHADOW
SYNCOSEL TB_CTR_ZERO Sync down-stream module
CMPCTL SHDWAMODE CC_SHADOW
SHDWBMODE CC_SHADOW
LOADAMODE CC_CTR_ZERO Load on CTR = 0
LOADBMODE CC_CTR_ZERO Load on CTR = 0
AQCTLA CAU AQ_SET Set actions for EPWM1A
CAD AQ_CLEAR
DBCTL MODE DB_FULL_ENABLE Enable Dead-band module
POLSEL DB_ACTV_HIC Active Hi complementary
DBFED DBFED 20 FED = 20 TBCLKs
DBRED 20 RED = 20 TBCLKs
Table 15-54. EPWM2 Initialization for Figure 15-66
Register Bit Value Comments
TBPRD TBPRD 450 (1C2h) Period = 900 TBCLK counts
TBPHS TBPHS 300 Phase = (300/900) × 360 = 120°
TBCTL CTRMODE TB_UPDOWN
PHSEN TB_ENABLE Slave module
PRDLD TB_SHADOW
SYNCOSEL TB_SYNC_IN Sync flow-through
PHSDIR TB_DOWN Count DOWN on sync
CMPCTL SHDWAMODE CC_SHADOW
SHDWBMODE CC_SHADOW
LOADAMODE CC_CTR_ZERO Load on CTR = 0
LOADBMODE CC_CTR_ZERO Load on CTR = 0
AQCTLA CAU AQ_SET Set actions for EPWM2A
CAD AQ_CLEAR
DBCTL MODE DB_FULL_ENABLE Enable Dead-band module
POLSEL DB_ACTV_HIC Active Hi complementary
DBFED DBFED 20 FED = 20 TBCLKs
DBRED 20 RED = 20 TBCLKs
1576
Pulse-Width Modulation Subsystem (PWMSS) SPRUH73H–October 2011–Revised April 2013
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