Enhanced PWM (ePWM) Module
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Table 15-56. EPWM1 Initialization for Figure 15-68
Register Bit Value Comments
TBPRD TBPRD 1200 (4B0h) Period = 1201 TBCLK counts
TBPHS TBPHS 0 Clear Phase Register to 0
TBCTL CTRMODE TB_UP
PHSEN TB_DISABLE Phase loading disabled
PRDLD TB_SHADOW
SYNCOSEL TB_CTR_ZERO Sync down-stream module
CMPA CMPA 600 (258h) Set 50% duty for EPWM1A
CMPCTL SHDWAMODE CC_SHADOW
SHDWBMODE CC_SHADOW
LOADAMODE CC_CTR_ZERO Load on CTR = 0
LOADBMODE CC_CTR_ZERO Load on CTR = 0
AQCTLA ZRO AQ_SET Set actions for EPWM1A
CAU AQ_CLEAR
DBCTL MODE DB_FULL_ENABLE Enable Dead-band module
POLSEL DB_ACTV_HIC Active Hi complementary
DBFED DBFED 50 FED = 50 TBCLKs
DBRED 70 RED = 70 TBCLKs
Table 15-57. EPWM2 Initialization for Figure 15-68
Register Bit Value Comments
TBPRD TBPRD 1200 (4B0h) Period = 1201 TBCLK counts
TBPHS TBPHS 0 Clear Phase Register to 0
TBCTL CTRMODE TB_UP
PHSEN TB_ENABLE Slave module
PRDLD TB_SHADOW
SYNCOSEL TB_SYNC_IN Sync flow-through
CMPA CMPA 600 (258h) Set 50% duty for EPWM2A
CMPCTL SHDWAMODE CC_SHADOW
SHDWBMODE CC_SHADOW
LOADAMODE CC_CTR_ZERO Load on CTR = 0
LOADBMODE CC_CTR_ZERO Load on CTR = 0
AQCTLA ZRO AQ_SET Set actions for EPWM2A
CAU AQ_CLEAR
DBCTL MODE DB_FULL_ENABLE Enable Dead-band module
POLSEL DB_ACTV_HIC Active Hi complementary
DBFED DBFED 30 FED = 30 TBCLKs
DBRED 40 RED = 40 TBCLKs
Example 15-8. Code Snippet for Configuration in Figure 15-68
// Run Time (Note: Example execution of one run-time instance)
//============================================================
EPwm2Regs.TBPHS = 1200-300; // Set Phase reg to 300/1200 * 360 = 90 deg
EPwm1Regs.DBFED = FED1_NewValue; // Update ZVS transition interval
EPwm1Regs.DBRED = RED1_NewValue; // Update ZVS transition interval
EPwm2Regs.DBFED = FED2_NewValue; // Update ZVS transition interval
EPwm2Regs.DBRED = RED2_NewValue; // Update ZVS transition interval
1580
Pulse-Width Modulation Subsystem (PWMSS) SPRUH73H–October 2011–Revised April 2013
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