www.ti.com
ARM Cortex-A8 Memory Map
Table 2-3. L4_PER Peripheral Memory Map (continued)
Device Name Start_address (hex) End_address (hex) Size Description
0x4801_1000 0x4801_1FFF 4KB Reserved
Reserved 0x4801_2000 0x4801_3FFF 8KB Reserved
Reserved 0x4801_4000 0x4801_FFFF 48KB Reserved
Reserved 0x4802_0000 0x4802_0FFF 4KB Reserved
0x4802_1000 0x4802_1FFF 4KB Reserved
UART1 0x4802_2000 0x4802_2FFF 4KB UART1 Registers
0x4802_3000 0x4802_3FFF 4KB Reserved
UART2 0x4802_4000 0x4802_4FFF 4KB UART2 Registers
0x4802_5000 0x4802_5FFF 4KB Reserved
Reserved 0x4802_6000 0x4802_7FFF 8KB Reserved
Reserved 0x4802_8000 0x4802_8FFF 4KB Reserved
0x4802_9000 0x4802_9FFF 4KB Reserved
I2C1 0x4802_A000 0x4802_AFFF 4KB I2C1 Registers
0x4802_B000 0x4802_BFFF 4KB Reserved
Reserved 0x4802_C000 0x4802_CFFF 4KB Reserved
0x4802_D000 0x4802_DFFF 4KB Reserved
Reserved 0x4802_E000 0x4802_EFFF 4KB Reserved
0x4802_F000 0x4802_FFFF 4KB Reserved
McSPI0 0x4803_0000 0x4803_0FFF 4KB McSPI0 Registers
0x4803_1000 0x4803_1FFF 4KB Reserved
Reserved 0x4803_2000 0x4803_2FFF 4KB Reserved
0x4803_3000 0x4803_3FFF 4KB Reserved
Reserved 0x4803_4000 0x4803_4FFF 4KB Reserved
0x4803_5000 0x4803_5FFF 4KB Reserved
Reserved 0x4803_6000 0x4803_6FFF 4KB Reserved
0x4803_7000 0x4803_7FFF 4KB Reserved
McASP0 CFG 0x4803_8000 0x4803_9FFF 8KB McASP0 CFG Registers
0x4803_A000 0x4803_AFFF 4KB Reserved
Reserved 0x4803_B000 0x4803_BFFF 4KB Reserved
McASP1 CFG 0x4803_C000 0x4803_DFFF 8KB McASP1 CFG Registers
0x4803_E000 0x4803_EFFF 4KB Reserved
Reserved 0x4803_F000 0x4803_FFFF 4KB Reserved
DMTIMER2 0x4804_0000 0x4804_0FFF 4KB DMTimer2 Registers
0x4804_1000 0x4804_1FFF 4KB Reserved
DMTIMER3 0x4804_2000 0x4804_2FFF 4KB DMTimer3 Registers
0x4804_3000 0x4804_3FFF 4KB Reserved
DMTIMER4 0x4804_4000 0x4804_4FFF 4KB DMTimer4 Registers
0x4804_5000 0x4804_5FFF 4KB Reserved
DMTIMER5 0x4804_6000 0x4804_6FFF 4KB DMTimer5 Registers
0x4804_7000 0x4804_7FFF 4KB Reserved
DMTIMER6 0x4804_8000 0x4804_8FFF 4KB DMTimer6 Registers
0x4804_9000 0x4804_9FFF 4KB L4 Interconnect
DMTIMER7 0x4804_A000 0x4804_AFFF 4KB DMTimer7 Registers
0x4804_B000 0x4804_BFFF 4KB Reserved
GPIO1 0x4804_C000 0x4804_CFFF 4KB GPIO1 Registers
0x4804_D000 0x4804_DFFF 4KB Reserved
Reserved 0x4804_E000 0x4804_FFFF 8KB Reserved
159
SPRUH73H–October 2011–Revised April 2013 Memory Map
Submit Documentation Feedback
Copyright © 2011–2013, Texas Instruments Incorporated
To Next Page
Loading...
Need help?
General
