For Each IN Packet
Requested in
SETUP Phase
ReqPkt Set?
Yes
IN Token Sent
STALL
Received?
Yes
RxStall Set
ReqPkt Cleared
Error Count Cleared
Interrupt Generated
Problem in Data Sent
No
No
NAK
Received?
No
Yes
No
NAK Limit
Reached?
Yes
Yes
No
No
NAK Timeout Set
Endpoint Halted
Interrupt Generated
DATA0/1
Received?
Error Count
Incremented
ACK Sent
RxPktRdy Set
Transaction
Complete
Implies Problem at
Peripheral End of
Connection
Transaction Deemed
Completed
Error Bit Set
ReqPkt Cleared
Error Count Cleared
Interrupt Generated
Yes
Error Count
= 3?
ReqPkt Cleared
Error Count Cleared
Interrupt Generated
Error Count
Cleared
www.ti.com
Functional Description
If ERROR is set, it means that the controller has tried to send the required IN token three times without
getting any response. If NAK_TIMEOUT bit is set, it means that the controller has received a NAK
response to each attempt to send the IN token, for longer than the time set in HOST_NAKLIMIT0. The
controller can then be directed either to continue trying this transaction (until it times out again) by
clearing the NAK_TIMEOUT bit or to abort the transaction by clearing REQPKT before clearing the
NAK_TIMEOUT bit
4. If RXPKTRDY has been set, the software should read the data from the Endpoint 0 FIFO, then clear
RXPKTRDY.
5. If further data is expected, the software should repeat Steps 1-4.
When all the data has been successfully received, the CPU should proceed to the OUT Status Phase of
the Control Transaction.
Figure 16-9. Flow Chart of Data Stage (IN Data Phase) of a Control Transfer in Host Mode
16.3.8.2.1.3 Data Phase (OUT Data Phase) of a Control Transaction: Host Mode
For the OUT Data Phase of a control transaction (Figure 16-10), the software driving the USB host device
needs to:
1721
SPRUH73H–October 2011–Revised April 2013 Universal Serial Bus (USB)
Submit Documentation Feedback
Copyright © 2011–2013, Texas Instruments Incorporated
To Next Page
Loading...
Need help?
General
