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Functional Description
1. Set STATUSPKT and TXPKTRDY bits of HOST_CSR0 (bit 6 and bit 1, respectively).
NOTE: These bits need to be set together
2. Wait while the controller sends the OUT token and a zero-length DATA1 packet.
3. At the end of the attempt to send the data, the controller will generate an Endpoint 0 interrupt. The
software should then read HOST_CSR0 to establish whether the RXSTALL bit (bit 2), the ERROR bit
(bit 4) or the NAK_TIMEOUT bit (bit 7) has been set.
If RXSTALL bit is set, it indicates that the target could not complete the command and so has issued a
STALL response.
If ERROR bit is set, it means that the controller has tried to send the STATUS Packet and the following
data packet three times without getting any response.
If NAK_TIMEOUT bit is set, it means that the controller has received a NAK response to each attempt
to send the IN token, for longer than the time set in the HOST_NAKLIMIT0 register. The controller can
then be directed either to continue trying this transaction (until it times out again) by clearing the
NAK_TIMEOUT bit or to abort the transaction by flushing the FIFO before clearing the NAK_TIMEOUT
bit.
4. If none of RXSTALL, ERROR or NAK_TIMEOUT bits is set, the STATUS Phase has been correctly
ACKed.
1725
SPRUH73H–October 2011–Revised April 2013 Universal Serial Bus (USB)
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