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Functional Description
An interrupt is generated whenever a packet is sent and the software may use this interrupt to load the
next packet into the FIFO and set the TXPKTRDY bit in the HOST_TXCSR register (bit 0) in the same
way as for a Bulk Tx endpoint. As the interrupt could occur almost any time within a frame, depending on
when the host has scheduled the transaction, this may result in irregular timing of FIFO load requests. If
the data source for the endpoint is coming from some external hardware, it may be more convenient to
wait until the end of each frame before loading the FIFO as this will minimize the requirement for
additional buffering. This can be done by using the SOF_PULSE signal from the controller to trigger the
loading of the next data packet. The SOF_PULSE is generated once per frame(/microframe). The
interrupts may still be used to set the TXPKTRDY bit in HOST_TXCSR.
1733
SPRUH73H–October 2011–Revised April 2013 Universal Serial Bus (USB)
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