0
CPPI Packet
Packet Descriptor
Buffer pointer
Buffer size (256)
Next descriptor pointer
Buffer Descriptor
Buffer pointer
Buffer size (256)
Next descriptor pointer
Buffer Descriptor
Buffer size (96)
Packet size (608)
Data
Buffer
(Valid
data)
Data
Buffer
(Valid
data)
Data
Buffer
(Valid
data)
PBD(1)
PBD(2)
PPD
PPD PBD(1) PBD(2)
. . .
TailHead
Queue 93: USB0 EP1 TXCQ
. . . . . . . . . . . .
TailHead
Queue 32: USB0 EP1 TXSQ
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Functional Description
Figure 16-18. Transmit Descriptors and Queue Status Configuration
16.3.9.9.1.1 Transmit Initialization (Step 1)
The CPU performs the following steps for transmit initialization:
1. Initializes Memory Region 0 base address and Memory Region 0 size, Link RAM0 Base address, Link
RAM0 data size, and Link RAM1 Base address.
2. Creates PD, BDs, and DBs in main memory and link as indicated in Figure 16-19.
3. Initializes and configures the Queue Manager, Channel Setup, DMA Scheduler, and Mentor USB 2.0
Core.
4. Adds (pushes) the PPD and the two PBDs to the TXSQ by writing the Packet Descriptor address to the
TXSQ CTRL D Register.
Figure 16-19 captures the BD/DB pair in main memory and later submitted within the TXSQ.
1753
SPRUH73H–October 2011–Revised April 2013 Universal Serial Bus (USB)
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