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8-73. CM_PER_SPINLOCK_CLKCTRL Register .......................................................................... 601
8-74. CM_PER_MAILBOX0_CLKCTRL Register........................................................................... 602
8-75. CM_PER_L4HS_CLKSTCTRL Register.............................................................................. 603
8-76. CM_PER_L4HS_CLKCTRL Register ................................................................................. 604
8-77. CM_PER_OCPWP_L3_CLKSTCTRL Register ...................................................................... 605
8-78. CM_PER_OCPWP_CLKCTRL Register.............................................................................. 606
8-79. CM_PER_PRU_ICSS_CLKSTCTRL Register ....................................................................... 607
8-80. CM_PER_CPSW_CLKSTCTRL Register............................................................................. 608
8-81. CM_PER_LCDC_CLKSTCTRL Register ............................................................................. 609
8-82. CM_PER_CLKDIV32K_CLKCTRL Register.......................................................................... 610
8-83. CM_PER_CLK_24MHZ_CLKSTCTRL Register ..................................................................... 611
8-84. CM_WKUP_CLKSTCTRL Register.................................................................................... 615
8-85. CM_WKUP_CONTROL_CLKCTRL Register ........................................................................ 617
8-86. CM_WKUP_GPIO0_CLKCTRL Register ............................................................................. 618
8-87. CM_WKUP_L4WKUP_CLKCTRL Register .......................................................................... 619
8-88. CM_WKUP_TIMER0_CLKCTRL Register............................................................................ 620
8-89. CM_WKUP_DEBUGSS_CLKCTRL Register ........................................................................ 621
8-90. CM_L3_AON_CLKSTCTRL Register ................................................................................. 622
8-91. CM_AUTOIDLE_DPLL_MPU Register................................................................................ 623
8-92. CM_IDLEST_DPLL_MPU Register.................................................................................... 624
8-93. CM_SSC_DELTAMSTEP_DPLL_MPU Register .................................................................... 625
8-94. CM_SSC_MODFREQDIV_DPLL_MPU Register.................................................................... 626
8-95. CM_CLKSEL_DPLL_MPU Register................................................................................... 627
8-96. CM_AUTOIDLE_DPLL_DDR Register................................................................................ 628
8-97. CM_IDLEST_DPLL_DDR Register.................................................................................... 629
8-98. CM_SSC_DELTAMSTEP_DPLL_DDR Register .................................................................... 630
8-99. CM_SSC_MODFREQDIV_DPLL_DDR Register .................................................................... 631
8-100. CM_CLKSEL_DPLL_DDR Register ................................................................................... 632
8-101. CM_AUTOIDLE_DPLL_DISP Register ............................................................................... 633
8-102. CM_IDLEST_DPLL_DISP Register ................................................................................... 634
8-103. CM_SSC_DELTAMSTEP_DPLL_DISP Register.................................................................... 635
8-104. CM_SSC_MODFREQDIV_DPLL_DISP Register.................................................................... 636
8-105. CM_CLKSEL_DPLL_DISP Register................................................................................... 637
8-106. CM_AUTOIDLE_DPLL_CORE Register.............................................................................. 638
8-107. CM_IDLEST_DPLL_CORE Register .................................................................................. 639
8-108. CM_SSC_DELTAMSTEP_DPLL_CORE Register .................................................................. 640
8-109. CM_SSC_MODFREQDIV_DPLL_CORE Register .................................................................. 641
8-110. CM_CLKSEL_DPLL_CORE Register ................................................................................. 642
8-111. CM_AUTOIDLE_DPLL_PER Register ................................................................................ 643
8-112. CM_IDLEST_DPLL_PER Register .................................................................................... 644
8-113. CM_SSC_DELTAMSTEP_DPLL_PER Register..................................................................... 645
8-114. CM_SSC_MODFREQDIV_DPLL_PER Register .................................................................... 646
8-115. CM_CLKDCOLDO_DPLL_PER Register............................................................................. 647
8-116. CM_DIV_M4_DPLL_CORE Register.................................................................................. 648
8-117. CM_DIV_M5_DPLL_CORE Register.................................................................................. 649
8-118. CM_CLKMODE_DPLL_MPU Register................................................................................ 650
8-119. CM_CLKMODE_DPLL_PER Register ................................................................................ 652
8-120. CM_CLKMODE_DPLL_CORE Register .............................................................................. 653
8-121. CM_CLKMODE_DPLL_DDR Register ................................................................................ 655
22
List of Figures SPRUH73H–October 2011–Revised April 2013
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