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GPMC
Table 7-5. GPMC Pin Multiplexing Options (continued)
Non Multiplexed Non Multiplexed Multiplexed
16-Bit NAND
GPMC Signal Address Data 16- Address Data 8-Bit Address Data 16- 8-Bit NAND Device
Device
Bit Device
(1)
Device Bit Device
(1)
GPMC_AD[4] D4 D4 A/D[4] D4 D4
GPMC_AD[3] D3 D3 A/D[3] D3 D3
GPMC_AD[2] D2 D2 A/D[2] D2 D2
GPMC_AD[1] D1 D1 A/D[1] D1 D1
GPMC_AD[0] D0 D0 A/D[0] D0 D0
GPMC_CS[0]n CS0n (Chip Select) CS0n (Chip Select) CS0n (Chip Select) CE0n (Chip Enable) CE0n (Chip Enable)
GPMC_CS[1]n CS1n CS1n CS1n CE1n CE1n
GPMC_CS[2]n CS2n CS2n CS2n CE2n CE2n
GPMC_CS[3]n CS3n CS3n CS3n CE3n CE3n
GPMC_CS[4]n CS4n CS4n CS4n CE4n CE4n
GPMC_CS[5]n CS5n CS5n CS5n CE5n CE5n
GPMC_CS[6]n CS6n CS6n CS6n CE6n CE6n
ADVn (Address ADVn (Address ADVn (Address ALE (address latch ALE (address latch
GPMC_ADVn_ALE
Value) Value) Value) enable) enable)
CLE (command CLE (command
GPMC_BE0n_CLE BE0n (Byte Enable) BE0n (Byte Enable) BE0n (Byte Enable)
latch enable) latch enable)
GPMC_BE1n BE1n BE1n BE1n
GPMC_CLK CLK CLK CLK
OEn (Output OEn (Output OEn (Output
GPMC_OE_REn REn (read enable) REn (read enable)
Enable) Enable) Enable)
GPMC_WAIT0 WAIT0 WAIT0 WAIT0 R/B0n (ready/busy) R/B0n (ready/busy)
GPMC_WAIT1 WAIT1 WAIT1 WAIT1 R/B1n (ready/busy) R/B1n (ready/busy)
GPMC_WEn WEn (Write Enable) WEn (Write Enable) WEn (Write Enable) WEn (write enable) WEn (write enable)
GPMC_WPn WPn (Write Protect) WPn (Write Protect) WPn (Write Protect) WPn (write protect) WPn (write protect)
With all device types, the GPMC does not drive unnecessary address lines. They stay at their reset value
of 00.
Address mapping supports address/data-multiplexed 16-bit wide devices:
• The NOR flash memory controller still supports non-multiplexed address and data memory devices.
• Multiplexing mode can be selected through the GPMC_CONFIG1_i[9-8] MUXADDDATA bit field.
• Asynchronous page mode is not supported for multiplexed address and data devices.
257
SPRUH73H–October 2011–Revised April 2013 Memory Subsystem
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