Valid Address
D0 D1 D2 D3
OUT
IN
OUT
CSONTIME
ADVONTIME
ADVRDOFFTIME
OEONTIME
OEOFFTIME0
CLKACTIVATIONTIME
CSRDOFFTIME0
Wait deasserted one
GPMC.CLK cycle
before valid data
Wait deasserted
same cycle as
valid data
RDACCESSTIME
RDCYCLETIME0
PAGEBURSTACCESSTIME
PAGEBURSTACCESSTIME
PAGEBURSTACCESSTIME
RDCYCLETIME1
WAITMONITORINGTIME = 0b00
WAITMONITORINGTIME = 0b01
GPMC_FCLK
GPMC_CLK
nBE1/nBE0
nCS
nADV
nOE
DIR
WAIT
A[27:1]
A[16:1]/D[15:0]
CSRDOFFTIME1
OEOFFTIME1
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GPMC
Figure 7-8. Wait Behavior During a Synchronous Read Burst Access
The WAIT signal is active low. WAITMONITORINGTIME = 00b or 01b.
7.1.3.3.8.3.5 Wait Monitoring During a Synchronous Write Access
During synchronous accesses with wait-pin monitoring enabled (the WAITWRITEMONITORING bit), the
wait pin is captured synchronously with GPMC_CLK, using the rising edge of this clock.
If enabled, external wait-pin monitoring can be used in combination with WRACCESSTIME to delay the
effective memory device GPMC_CLK capture edge.
Wait-monitoring pipelining depth is similar to synchronous read access:
• At WRACCESSTIME completion if WAITMONITORINGTIME = 0
• In the WAITMONITORINGTIME x (GPMCFCLKDIVIDER + 1) GPMC_FCLK cycles before
WRACCESSTIME completion if WAITMONITORINGTIME not equal to 0.
269
SPRUH73H–October 2011–Revised April 2013 Memory Subsystem
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