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Table 17-56. IRQENABLE_CLR_3 Register Field Descriptions (continued)
Bit Field Type Reset Description
6 NewMSGStatusUuMB3 R/W 0h
New Message Status bit for User u, Mailbox 3
0 = NoAction : No action
1 = SetEvent : Set the event (for debug)
5 NotFullStatusUuMB2 R/W 0h
Not Full Status bit for User u, Mailbox 2
0 = NoAction : No action
1 = SetEvent : Set the event (for debug)
4 NewMSGStatusUuMB2 R/W 0h
New Message Status bit for User u, Mailbox 2
0 = NoAction : No action
1 = SetEvent : Set the event (for debug)
3 NotFullStatusUuMB1 R/W 0h
Not Full Status bit for User u, Mailbox 1
0 = NoAction : No action
1 = SetEvent : Set the event (for debug)
2 NewMSGStatusUuMB1 R/W 0h
New Message Status bit for User u, Mailbox 1
0 = NoAction : No action
1 = SetEvent : Set the event (for debug)
1 NotFullStatusUuMB0 R/W 0h
Not Full Status bit for User u, Mailbox 0
0 = NoAction : No action
1 = SetEvent : Set the event (for debug)
0 NewMSGStatusUuMB0 R/W 0h
New Message Status bit for User u, Mailbox 0
0 = NoAction : No action
1 = SetEvent : Set the event (for debug)
3305
SPRUH73H–October 2011–Revised April 2013 Interprocessor Communication
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