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Functional Description
To reset the autobauding hardware (to start a new AT detection) or to set the UART in standard mode (no
autobaud), the UARTi.UART_MDR1[2:0] MODE_ SELECT bit field must be set to reset state (0x7) and
then to the UART in autobauding mode (0x2) or to the UART in standard mode (0x0).
Use limitation:
• Only 7- and 8-bit characters (5- and 6-bit not supported)
• 7-bit character with space parity not supported
• Baud rate between 1200 and 115,200 bps (10 possibilities)
19.3.8.1.3.5 Error Detection
When the UARTi.UART_LSR register is read, the UARTi.UART_LSR[4:2] bit field reflects the error bits
(BI: break condition, FE: framing error, PE: parity error) of the character at the top of the RX FIFO (the
next character to be read). Therefore, reading the UARTi.UART_LSR register and then reading the
UARTi.UART_RHR register identifies errors in a character.
Reading the UARTi.UART_RHR register updates the BI, FE, and PE bits (see Table 19-11 for the UART
mode interrupts).
The UARTi.UART_LSR[7] RX_FIFO_STS bit is set when there is an error in the RX FIFO and is cleared
only when no errors remain in the RX FIFO.
NOTE: Reading the UARTi.UART_LSR register does not cause an increment of the RX FIFO read
pointer. The RX FIFO read pointer is incremented by reading the UARTi.UART_RHR
register.
Reading the UARTi.UART_LSR register clears the OE bit if it is set (see Table 19-11 for the UART mode
interrupts).
19.3.8.1.3.6 Overrun During Receive
Overrun during receive occurs if the RX state-machine tries to write data into the RX FIFO when it is
already full. When overrun occurs, the device interrupts the MPU with the UARTi.UART_IIR[5:1] IT_TYPE
bit field set to 0x3 (receiver line status error) and discards the remaining portion of the frame.
Overrun also causes an internal flag to be set, which disables further reception. Before the next frame can
be received, the MPU must:
• Reset the RX FIFO.
• Read the UARTi.UART_RESUME register, which clears the internal flag.
19.3.8.1.3.7 Time-Out and Break Conditions
19.3.8.1.3.7.1 Time-Out Counter
An RX idle condition is detected when the receiver line (uarti_rx) is high for a time that equals 4x the
programmed word length + 12 bits. uarti_rx is sampled midway through each bit.
For sleep mode, the counter is reset when there is activity on uarti_rx.
For the time-out interrupt, the counter counts only when there is data in the RX FIFO, and the count is
reset when there is activity on uarti_rx or when the UARTi.UART_RHR register is read.
19.3.8.1.3.7.2 Break Condition
When a break condition occurs, uarti_tx is pulled low. A break condition is activated by setting the
UARTi.UART_LCR[6] BREAK_EN bit. The break condition is not aligned on word stream (a break
condition can occur in the middle of a character). The only way to send a break condition on a full
character is:
1. Reset the TX FIFO (if enabled).
2. Wait for the transmit shift register to empty (the UARTi.UART_LSR[6] TX_SR_E bit is set to 1).
3479
SPRUH73H–October 2011–Revised April 2013 Universal Asynchronous Receiver/Transmitter (UART)
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