0.25 or 1/4 duty cycle pulse
0.33 or 1/3 duty cycle pulse
0.42 or 5/12 duty cycle pulse
0.5 or 1/2 duty cycle pulse
12x BAUD
multiple
"01" "011"
T T T T T
Effective T length
Nominal T
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Functional Description
Figure 19-31. CIR Pulse Modulation
A minimum of 4 modulation pulses per bit is required by the module.
Based on the requested modulation frequency, the CFPS register must be set with the correct dividing
value to provide the more accurate pulse frequency:
Dividing value = (FCLK/12)/MODfreq
Where FCLK = System clock frequency (48 MHz)
12 = real value of BAUD multiple
MODfreq = Effective frequency of the modulation (MHz)
Example: For a targeted modulation frequency of 36 kHz, the CFPS value must be set to 111 in
decimal which provide an modulation frequency of 36.04 kHz.
Note: The CFPS register is to start with a reset value of 105 (decimal) which translates to a frequency
of 38.1 kHz.
The duty cycle of these pulses is user defined by the pulse duty register bits in the MDR2 configuration
register.
MDR2[5:4] Duty Cycle (High Level)
00 1/4
01 1/3
10 5/12
11 1/2
Figure 19-32. CIR Modulation Duty Cycle
3493
SPRUH73H–October 2011–Revised April 2013 Universal Asynchronous Receiver/Transmitter (UART)
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