I2C Registers
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Table 21-15. I2C_IRQENABLE_CLR Register Field Descriptions (continued)
Bit Field Type Reset Description
6 STC_IE R/W 0h Start condition interrupt enable clear.
Mask or unmask the interrupt signaled by bit in I2C_STAT[STC].
0x0 = Start condition interrupt disabled
0x1 = Start condition interrupt enabled
5 GC_IE R/W 0h General call interrupt enable clear.
Mask or unmask the interrupt signaled by bit in I2C_STAT[GC].
0x0 = General call interrupt disabled
0x1 = General call interrupt enabled
4 XRDY_IE R/W 0h Transmit data ready interrupt enable clear.
Mask or unmask the interrupt signaled by bit in I2C_STAT[XRDY].
0x0 = Transmit data ready interrupt disabled
0x1 = Transmit data ready interrupt enabled
3 RRDY_IE R/W 0h Receive data ready interrupt enable set.
Mask or unmask the interrupt signaled by bit in I2C_STAT[RRDY]
0x0 = Receive data ready interrupt disabled
0x1 = Receive data ready interrupt enabled
2 ARDY_IE R/W 0h Register access ready interrupt enable clear.
Mask or unmask the interrupt signaled by bit in I2C_STAT[ARDY].
0x0 = Register access ready interrupt disabled
0x1 = Register access ready interrupt enabled
1 NACK_IE R/W 0h No acknowledgment interrupt enable clear.
Mask or unmask the interrupt signaled by bit in I2C_STAT[NACK].
0x0 = Not Acknowledge interrupt disabled
0x1 = Not Acknowledge interrupt enabled
0 AL_IE R/W 0h Arbitration lost interrupt enable clear.
Mask or unmask the interrupt signaled by bit in I2C_STAT[AL].
0x0 = Arbitration lost interrupt disabled
0x1 = Arbitration lost interrupt enabled
3732
I2C SPRUH73H–October 2011–Revised April 2013
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