GPMC
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Table 7-65. GPMC_CONFIG1_i Field Descriptions (continued)
Bit Field Value Description
22 WAITREADMONITORING Selects the Wait monitoring configuration for Read accesses
0 WAIT pin is not monitored for read accesses
1 WAIT pin is monitored for read accesses
21 WAITWRITEMONITORING Selects the Wait monitoring configuration for Write accesses
0 WAIT pin is not monitored for write accesses
1 WAIT pin is monitored for write accesses
20 Reserved 0 Reserved
19-18 WAITMONITORINGTIME Selects input pin Wait monitoring time
0 WAIT pin is monitored with valid data
1h WAIT pin is monitored one GPMC_CLK cycle before valid data
2h WAIt pin is monitored two GPMC_CLK cycle before valid data
3h Reserved
17-16 WAITPINSELECT Selects the input WAIT pin for this chip select
0 WAIT input pin is WAIT0
1h WAIT input pin is WAIT1
2h Reserved
3h Reserved
15-14 Reserved 0 Reserved
13-12 DEVICESIZE Selects the device size attached.
0 8 bit
1h 16 bit
2h Reserved
3h Reserved
11-10 DEVICETYPE Selects the attached device type
0 NOR Flash like, asynchronous and synchronous devices
1h Reserved
2h NAND Flash like devices, stream mode
3h Reserved
9-8 MUXADDDATA Enables the Address and data multiplexed protocol (Reset value is
SYSBOOT[11:10] input pin sampled at IC reset for CS[0] and 0 for CS[1-6])
0 Non-multiplexed attached device
1h AAD-multiplexed protocol device
2h Address and data multiplexed attached device
3h Reserved
7-5 Reserved 0 Reserved
4 TIMEPARAGRANULARITY Signals timing latencies scalar factor (Rd/WRCycleTime, AccessTime,
PageBurstAccessTime, CSOnTime, CSRd/WrOffTime, ADVOnTime,
ADVRd/WrOffTime, OEOnTime, OEOffTime, WEOnTime, WEOffTime,
Cycle2CycleDelay, BusTurnAround, TimeOutStartValue)
0 ×1 latencies
1 ×2 latencies
3-2 Reserved 0 Reserved
1-0 GPMCFCLKDIVIDER Divides the GPMC.FCLK clock
0 GPMC_CLK frequency = GPMC_FCLK frequency
1h GPMC_CLK frequency = GPMC_FCLK frequency/2
2h GPMC_CLK frequency = GPMC_FCLK frequency/3
3h GPMC_CLK frequency = GPMC_FCLK frequency/4
376
Memory Subsystem SPRUH73H–October 2011–Revised April 2013
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