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Functional Description
The following actions are taken if a clock failure is detected:
1. Transmit clock failure flag (XCKFAIL) in XSTAT is set. This causes an interrupt if transmit clock failure
interrupt enable bit (XCKFAIL) in XINTCTL is set.
In addition (only supported for DIT mode), if the transmit clock failure detect autoswitch enable bit
(XCKFAILSW) in XCLKCHK is set, the following additional steps are taken to change the clock source
from external to internal:
1. High-frequency transmit clock source bit (HCLKXM) in AHCLKXCTL is set to 1 and internal serial clock
divider is selected. However, AHCLKX pin direction does not change to an output while XCKFAIL is
set.
2. The internal clock divider is reset, so that the next clock it produces is a full period. However, the
transmit clock divide ratio bits (HCLKXDIV) in AHCLKXCTL are not affected, so the internal clock
divider generates clocks at the rate configured.
3. The transmit section is reset for a single serial clock period.
4. The transmit section is released from reset and attempts to begin transmitting. If data is available, it
begins transmitting immediately; otherwise, it enters the underrun state. An initial underrun is certain to
occur, the pattern 1100 (BMC zeroes) should be shifted out initially.
To change back to an external clock, take the following actions:
1. Wait for the external clock to stabilize again. This can be checked by polling the transmit clock count
(XCNT) in XCLKCHK.
2. Reset the transmit section according to the startup procedure in Section 22.3.10.4.6.1.
3813
SPRUH73H–October 2011–Revised April 2013 Multichannel Audio Serial Port (McASP)
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