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McASP Registers
Table 22-16. Pin Data Output Register (PDOUT) Field Descriptions
Bit Field Value Description
31 AFSR Determines drive on AFSR output pin when the corresponding PFUNC[31] and PDIR[31] bits are set to 1.
0 Pin drives low.
1 Pin drives high.
30 AHCLKR Determines drive on AHCLKR output pin when the corresponding PFUNC[30] and PDIR[30] bits are set to
1.
0 Pin drives low.
1 Pin drives high.
29 ACLKR Determines drive on ACLKR output pin when the corresponding PFUNC[29] and PDIR[29] bits are set to 1.
0 Pin drives low.
1 Pin drives high.
28 AFSX Determines drive on AFSX output pin when the corresponding PFUNC[28] and PDIR[28] bits are set to 1.
0 Pin drives low.
1 Pin drives high.
27 AHCLKX Determines drive on AHCLKX output pin when the corresponding PFUNC[27] and PDIR[27] bits are set to
1.
0 Pin drives low.
1 Pin drives high.
26 ACLKX Determines drive on ACLKX output pin when the corresponding PFUNC[26] and PDIR[26] bits are set to 1.
0 Pin drives low.
1 Pin drives high.
25 AMUTE Determines drive on AMUTE output pin when the corresponding PFUNC[25] and PDIR[25] bits are set to
1.
0 Pin drives low.
1 Pin drives high.
24-6 Reserved 0 Reserved. The reserved bit location always returns the default value. A value written to this field has no
effect. If writing to this field, always write the default value for future device compatibility.
5-0 AXR[5-0] Determines drive on AXR[n] output pin when the corresponding PFUNC[n] and PDIR[n] bits are set to 1.
0 Pin drives low.
1 Pin drives high.
3835
SPRUH73H–October 2011–Revised April 2013 Multichannel Audio Serial Port (McASP)
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