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McASP Registers
Table 22-17. Pin Data Input Register (PDIN) Field Descriptions
Bit Field Value Description
31 AFSR Logic level on AFSR pin.
0 Pin is logic low.
1 Pin is logic high.
30 AHCLKR Logic level on AHCLKR pin.
0 Pin is logic low.
1 Pin is logic high.
29 ACLKR Logic level on ACLKR pin.
0 Pin is logic low.
1 Pin is logic high.
28 AFSX Logic level on AFSX pin.
0 Pin is logic low.
1 Pin is logic high.
27 AHCLKX Logic level on AHCLKX pin.
0 Pin is logic low.
1 Pin is logic high.
26 ACLKX Logic level on ACLKX pin.
0 Pin is logic low.
1 Pin is logic high.
25 AMUTE Logic level on AMUTE pin.
0 Pin is logic low.
1 Pin is logic high.
24-6 Reserved 0 Reserved. The reserved bit location always returns the default value. A value written to this field has no
effect. If writing to this field, always write the default value for future device compatibility.
5-0 AXR[5-0] Logic level on AXR[n] pin.
0 Pin is logic low.
1 Pin is logic high.
3837
SPRUH73H–October 2011–Revised April 2013 Multichannel Audio Serial Port (McASP)
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