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DCAN Registers
Table 23-14. CTL Register Field Descriptions (continued)
Bit Field Type Reset Description
19 DE2 R/W 0h Enable DMA request line for IF2.
Note: A pending DMA request for IF2 remains active until first
access to one of the IF2 registers.
0x0 = Disabled
0x1 = Enabled
18 DE1 R/W 0h Enable DMA request line for IF1.
Note: A pending DMA request for IF1 remains active until first
access to one of the IF1 registers.
0x0 = Disabled
0x1 = Enabled
17 IE1 R/W 0h
Interrupt line 1 enable
0x0 = Disabled - Module interrupt DCAN1INT is always low.
0x1 = Enabled - interrupts will assert line DCAN1INT to one; line
remains active until pending interrupts are processed.
16 InitDbg R 0h
Internal init state while debug access
0x0 = Not in debug mode, or debug mode requested but not
entered.
0x1 = Debug mode requested and internally entered; the DCAN is
ready for debug accesses.
15 SWR R/WP 0h SW reset enable.
Note: To execute software reset, the following procedure is
necessary: (a) Set Init bit to shut down CAN communication and (b)
Set SWR bit additionally to Init bit.
0x0 = Normal Operation
0x1 = Module is forced to reset state. This bit will automatically get
cleared after execution of SW reset after one OCP clock cycle.
14 Reserved R 0h
13-10 PMD R/W 5h Parity on/off.
5 = Parity function disabled.
Others = Parity function enabled.
9 ABO R/W 0h
Auto-Bus-On enable
0x0 = The Auto-Bus-On feature is disabled
0x1 = The Auto-Bus-On feature is enabled
8 IDS R/W 0h
Interruption debug support enable
0x0 = When Debug/Suspend mode is requested, DCAN will wait for
a started transmission or reception to be completed before entering
Debug/Suspend mode
0x1 = When Debug/Suspend mode is requested, DCAN will interrupt
any transmission or reception, and enter Debug/Suspend mode
immediately.
7 Test R/W 0h
Test mode enable
0x0 = Normal Operation
0x1 = Test Mode
6 CCE R/W 0h
Configuration change enable
0x0 = The CPU has no write access to the configuration registers.
0x1 = The CPU has write access to the configuration registers (when
Init bit is set).
5 DAR R/W 0h
Disable automatic retransmission
0x0 = Automatic retransmission of not successful messages
enabled.
0x1 = Automatic retransmission disabled.
4 Reserved R 0h
3925
SPRUH73H–October 2011–Revised April 2013 Controller Area Network (CAN)
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