DCAN Registers
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Table 23-52. IF2CMD Register Field Descriptions (continued)
Bit Field Type Reset Description
14 DMAactive R/WP 0h Activation of DMA feature for subsequent internal IF2 update.
Note: Due to the auto reset feature of the DMAactive bit, this bit has
to be set for each subsequent DMA cycle separately.
0x0 = DMA request line is independent of IF2 activities.
0x1 = DMA is requested after completed transfer between IF2
register set and message RAM. The DMA request remains active
until the first read or write to one of the IF2 registers; an exception is
a write to Message Number (Bits [7:0]) when DMAactive is one.
13-8 Reserved R 0h
7-0 Message_Number R/WP 0h
Number of message object in message RAM which is used for data
transfer.
0x00 = Invalid message number.
0x01 = Valid message numbers (values 01 to 80).
0x80 = Valid message number.
0x81 = Invalid message numbers (values 81 to FF).
0xff = Invalid message number.
3970
Controller Area Network (CAN) SPRUH73H–October 2011–Revised April 2013
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