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Table 7-144. DDR_PHY_CTRL_1_SHDW Register Field Descriptions (continued)
Bit Field Type Reset Description
4-0 reg_read_latency R/W 0h This field defines the latency for read data from DDR SDRAM in
number of DDR clock cycles.
The value applied should be equal to the required value minus one.
The maximum read latency supported by the DDR PHY is equal to
CAS latency plus 7 clock cycles.
The minimum read latency must be equal to CAS latency plus 2
clock cycle.
461
SPRUH73H–October 2011–Revised April 2013 Memory Subsystem
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