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ELM
Table 7-171. Use Case: Continuous Mode (continued)
Step Register/ Bit Field / Programming Model Value
Defines the error-correction level used: 8 bits ELM_LOCATION_CONFIG[1:0] ECC_BCH_LEVEL 0x1
Defines the maximum buffer length: 528 bytes ELM_LOCATION_CONFIG[26:16] ECC_SIZE 0x420
(2x528 = 1056)
Sets the ELM in continuous mode ELM_PAGE_CTRL 0
Enables interrupt for syndrome polynomial 0 ELM_IRQENABLE[0] LOCATION_MASK_0 0x1
Set the input syndrome polynomial 0. ELM_SYNDROME_FRAGMENT_0_i (i=0) 0xFB0D0980
ELM_SYNDROME_FRAGMENT_1_i (i=0) 0xE44F767B
ELM_SYNDROME_FRAGMENT_2_i (i=0) 0x16ABE115
ELM_SYNDROME_FRAGMENT_3_i (i=0) 0x0000000A
Initiates the computation process ELM_SYNDROME_FRAGMENT_6_i[16] 0x1
SYNDROME_VALID (i=0)
Wait until process is complete for syndrome
polynomial 0:
IRQ_ELM is generated or poll the status register.
Read that error-location process is complete for ELM_IRQSTATUS[0] LOC_VALID_0 0x1
syndrome polynomial 0.
Read the process exit status: ELM_LOCATION_STATUS_i[8] ECC_CORRECTABLE 0x1
All errors were successfully located. (i=0)
Read the number of errors: ELM_LOCATION_STATUS_i[4:0] ECC_NB_ERRORS (i=0) 0x4
Four errors detected.
Read the error-location bit addresses for syndrome ELM_ERROR_LOCATION_0_i (i=0) 0x1AF
polynomial 0 of the 4 first registers:
ELM_ERROR_LOCATION_1_i (i=0) 0x426
Errors are located in the data buffer at decimal
ELM_ERROR_LOCATION_2_i (i=0) 0x775
addresses 431, 1062, 1909, 3452.
ELM_ERROR_LOCATION_3_i (i=0) 0xD7C
Clear the corresponding interrupt for polynomial 0. ELM_IRQSTATUS[0] LOC_VALID_0 0x1
The NAND flash data in the sector are seen as a polynomial of degree 4223 (number of bits in a 528 byte
buffer minus 1), with each data bit being a coefficient in the polynomial. When reading from a NAND flash
using the GPMC module, computation of the polynomial syndrome assumes that the first NAND word read
at address 0x0 contains the highest-order coefficient in the message. Furthermore, in the 16-bit NAND
word, bits are ordered from bit 7 to bit 0, then from bit 15 to bit 8. Based on this convention, an address
table of the data buffer can be built. NAND memory addresses in Table 7-172 are given in decimal format.
483
SPRUH73H–October 2011–Revised April 2013 Memory Subsystem
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