PFD Multiplier
1/(N+1)
8 bits
1/M2
7 bits
4 bits
1/(SD)
8 bits
Sigma
delta
1/M.f
8 bits
HS1
HS2
DAC
SSC
CLKDCOLDO
CLKINP
CLKINPULOW
CLKOUT
CLKOUTLDO
SDCLK
FBCLK
CLKINP
REFCLK
SELFREQDCO
ULOWCLKEN
HS1: 2–1 GHz
HS2: 1–0.5 GHz
1/(N2 + 1)
Power, Reset, and Clock Management
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Figure 8-9. Basic Structure of the ADPLLLJ
The Peripheral PLL belongs to type ADPLLLJ:
The DPLL has two input clocks:
• CLKINP: Reference input clock
• CLKINPULOW: Bypass input clock.
The DPLL has two internal clocks:
• REFCLK (Internal reference clock): This is generated by dividing the input clock CLKINP by the
programmed value N+1. The entire loop of the PLL runs on the REFCLK.
Here, REFCLK = CLKINP/(N+1).
• CLKDCO (Internal Oscillator clock.):This is the raw clock directly out of the digitally controlled oscillator
(DCO) before the post-divider. The PLL output clock is synthesized by an internal oscillator which is
phase locked to the refclk. There are two oscillators built within ADPLLLJ. The oscillators are user
selectable based on the synthesized output clock frequency requirement. In locked condition, CLKDCO
= CLKINP *[M/(N+1)].
The ADPLLLJ lock frequency is defined as follows: f
DPLL
= (M * CLKINP)/(N+1)
The DPLL has three external output clocks:
• CLKOUTLDO: Primary output clock in VDDLDOOUT domain. Bypass option not available on this
output.
CLKOUTLDO = (M / (N+1))*CLKINP*(1/M2)
• CLKOUT:
Primary output clock on digital core domain
CLKOUT = (M / (N+1))*CLKINP*(1/M2)
• CLKDCOLDO:
Oscillator (DCO) output clock before post-division in VDDLDOOUT domain. Bypass option is not
available on this output.
CLKDCOLDO = (M / (N+1))*CLKINP.
522
Power, Reset, and Clock Management (PRCM) SPRUH73H–October 2011–Revised April 2013
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