Power, Reset, and Clock Management
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Table 8-25. Reset Sources
Cold Reset Sources Warm Reset sources
Characteristic Pin PORz SW Cold Reset Bad Device Pin Warm Reset Watchdog Timer SW Warm Reset TRSTz
Boot pins latched Y N N N N N N
Resets Standard Y N N N N N N
Efuses
Resets Customer Y Y Y Y Y Y N
Efuses
DRAM contents N N N Y
(1)
Y
(1)
Y
(1)
Y
preserved
Resets PLLs
(2)
Y Y Y N N N N
Resets Clock Y Y Y N N N N
Dividers
(2)
PLLs enter bypass Y Y Y Y Y Y N
mode
(2)
Reset source N N N Y Y Y Y
blockable by
emulation
Resets test and Y Y Y N N N N
emulation logic
Resets GMAC switch Y N
(3)
Y N
(3)
N
(3)
N
(3)
and related chip logic
Resets Chip Y Y Y Y Y Y N
Functional Logic
(4)
Puts IOs in Tri-state Y Y Y Y Y Y N
Resets Pinmux Y Y Y
(5)
Y
(5)
Y
(5)
Y
(5)
N
Registers
Reset out Assertion Y Y Y
(5)
Y
(5)
Y
(5)
Y
(5)
N
(nRESETIN_OUT
Pin)
Resets RTC N N N N N N N
(1)
The ROM software does not utilize this feature of DRAM content preservation. Hence, the AM335x re-boots like a cold boot for warm reset as well.
(2)
CORE PLL is an exception when EMAC switch reset isolation is enabled
(3)
Only true if GMAC switch reset isolation is enabled in control registers, otherwise will be reset.
(4)
There are exception details in control module & PRCM registers which are captured in the register specifications in Chapter 8 and Chapter 9. This includes some pinmux registers which
are warm reset in-sensitive.
(5)
Some special IOs/Muxing registers like test, emulation, GEMAC Switch (When under reset isolation mode), etc related will not be affected under warm reset conditions.
542
Power, Reset, and Clock Management (PRCM) SPRUH73H–October 2011–Revised April 2013
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