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Power, Reset, and Clock Management
Table 8-30. CM_PER_L4LS_CLKSTCTRL Register Field Descriptions (continued)
Bit Field Type Reset Description
19 CLKACTIVITY_GPIO_1_ R 1h
This field indicates the state of the GPIO1_GDBCLK clock in the
GDBCLK
domain.
0x0 = Inact : Corresponding clock is gated
0x1 = Act : Corresponding clock is active
18 Reserved R 1h
Reserved.
17 CLKACTIVITY_LCDC_GC R 0h
This field indicates the state of the LCD clock in the domain.
LK
0x0 = Inact : Corresponding clock is gated
0x1 = Act : Corresponding clock is active
16 CLKACTIVITY_TIMER4_ R 0h
This field indicates the state of the TIMER4 CLKTIMER clock in the
GCLK
domain.
0x0 = Inact : Corresponding clock is gated
0x1 = Act : Corresponding clock is active
15 CLKACTIVITY_TIMER3_ R 0h
This field indicates the state of the TIMER3 CLKTIMER clock in the
GCLK
domain.
0x0 = Inact : Corresponding clock is gated
0x1 = Act : Corresponding clock is active
14 CLKACTIVITY_TIMER2_ R 0h
This field indicates the state of the TIMER2 CLKTIMER clock in the
GCLK
domain.
0x0 = Inact : Corresponding clock is gated
0x1 = Act : Corresponding clock is active
13 CLKACTIVITY_TIMER7_ R 0h
This field indicates the state of the TIMER7 CLKTIMER clock in the
GCLK
domain.
0x0 = Inact : Corresponding clock is gated
0x1 = Act : Corresponding clock is active
12 Reserved R 0h
11 CLKACTIVITY_CAN_CLK R 0h
This field indicates the state of the CAN_CLK clock in the domain.
0x0 = Inact : Corresponding clock is gated
0x1 = Act : Corresponding clock is active
10 CLKACTIVITY_UART_GF R 0h
This field indicates the state of the UART_GFCLK clock in the
CLK
domain.
0x0 = Inact : Corresponding clock is gated
0x1 = Act : Corresponding clock is active
9 Reserved R 0h
8 CLKACTIVITY_L4LS_GC R 1h
This field indicates the state of the L4LS_GCLK clock in the domain.
LK
0x0 = Inact : Corresponding clock is gated
0x1 = Act : Corresponding clock is active
7-2 Reserved R 0h
1-0 CLKTRCTRL R/W 2h
Controls the clock state transition of the L4 SLOW clock domain in
PER power domain.
0x0 = NO_SLEEP : NO_SLEEP: Sleep transition cannot be initiated.
Wakeup transition may however occur.
0x1 = SW_SLEEP : SW_SLEEP: Start a software forced sleep
transition on the domain.
0x2 = SW_WKUP : SW_WKUP: Start a software forced wake-up
transition on the domain.
0x3 = Reserved : Reserved.
551
SPRUH73H–October 2011–Revised April 2013 Power, Reset, and Clock Management (PRCM)
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