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Power, Reset, and Clock Management
Table 8-166. CM_RTC REGISTERS
Offset Acronym Register Name Section
0h CM_RTC_RTC_CLKCTRL This register manages the RTC clocks. Section 8.1.12.6.1
4h CM_RTC_CLKSTCTRL This register enables the domain power state transition. Section 8.1.12.6.2
It controls the SW supervised clock domain state
transition between ON-ACTIVE and ON-INACTIVE
states.
It also hold one status bit per clock input of the domain.
693
SPRUH73H–October 2011–Revised April 2013 Power, Reset, and Clock Management (PRCM)
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