Power, Reset, and Clock Management
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Table 8-204. PRM_LDO_SRAM_MPU_SETUP Register Field Descriptions (continued)
Bit Field Type Reset Description
2 ABBOFF_SLEEP_EXPOR R/W 0h Determines whether SRAMNWA is supplied by VDDS or VDDAR
T during deep-sleep.
After PowerOn reset and Efuse sensing, this bitfield is automatically
loaded with an Efuse value from control module.
Bitfield remains writable after this.
0x0 = SRAMNW_SLP_VDDS : SRAMNWA supplied with VDDS
0x1(Read) = SRAMNW_SLP_VDDASRAMNWA supplied with
VDDAR
1 ABBOFF_ACT_EXPORT R/W 0h Determines whether SRAMNWA is supplied by VDDS or VDDAR
during active mode.
After PowerOn reset and Efuse sensing, this bitfield is automatically
loaded with an Efuse value from control module.
Bitfield remains writable after this.
0x0 = SRAMNW_ACT_VDDS : SRAMNWA supplied with VDDS
0x1(Read) = SRAMNW_ACT_VDDASRAMNWA supplied with
VDDAR
0 DISABLE_RTA_EXPORT R/W 0h Control for HD memory RTA feature.
After PowerOn reset and Efuse sensing, this bitfield is automatically
loaded with an Efuse value from control module.
Bitfield remains writable after this.
0x0 = RTA_ENABLED : HD memory RTA feature is enabled
0x1 = RTA_DISABLED : HD memory RTA feature is disabled
734
Power, Reset, and Clock Management (PRCM) SPRUH73H–October 2011–Revised April 2013
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