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EDMA3 Registers
Figure 11-61. QDMA Region Access Enable for Region m (QRAEm)32-bit, 2 Rows
31 16
Reserved
R-0
15 8 7 6 5 4 3 2 1 0
Reserved E7 E6 E5 E4 E3 E2 E1 E0
R-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 11-45. QDMA Region Access Enable for Region M (QRAEm) Field Descriptions
Bit Field Value Description
31-8 Reserved 0 Reserved. Always write 0 to this bit; writes of 1 to this bit are not supported and attempts to do so may
result in undefined behavior.
7-0 En QDMA region access enable for bit n/QDMA channel n in region m.
0 Accesses via region m address space to bit n in any QDMA channel register are not allowed. Reads
return 0 on bit n and writes do not modify the state of bit n.
1 Accesses via region m address space to bit n in any QDMA channel register are allowed. Reads return
the value from bit n and writes modify the state of bit n.
959
SPRUH73H–October 2011–Revised April 2013 Enhanced Direct Memory Access (EDMA)
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