Is any
SW?
• Generate END_OF_SEQUENCE int
• If pen down flag = 1 and now pen is up,
then generate PEN_UP interrupt and
reset pen_down_flag
No
Yes
*
HW event?
No
Yes
Increment N
If HW[N] and
StepEnable[N]
Apply StepConfig [N]
Wait OpenDelay [N]
Wait SampleDelay [N]
ADC Conversion
AVG[N]?
Looped all enabled
HW steps?
Apply StepConfig [N]
Wait OpenDelay [N]
Wait SampleDelay [N]
ADC Conversion
AVG[N]?
Looped all enabled
SW steps?
Yes
Yes
No
If sw[N] and
StepEnable[N]
No
No
Yes
Yes
(Reset StepEnable[n] if One-Shot[n])
(Reset StepEnable[n] if One-Shot[n])
If TS Charge step is enabled apply TS
Charge StepConfig and OpenDelay (ignore
any pen irq during this step)
Yes
StepEnable[N]=1?
Yes
No
IDLE
(apply Idle Step Config)
• If preempt flag =1, increment N,
else set N to first SW Stepconfig
• Reset Preempt flag
Reset pen override mask
Preemption
enabled?
No
Set preempt
flag =1;
Save N
Yes
* HW event can either be Pen touch, or input HW event, but not both
• Set N=0
• Set pen down flag = 1
• Set pen override mask = 1
• Ignore Pen IRQs
Incr N
Update Shadow
StepEnable Reg
Yes
No
Ifpreempt flag is 1, restore N, elseset N
to first SW Stepconfig
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Operational Modes
Figure 12-3. Sequencer FSM
The previous diagram does not actually represent clock cycles but instead illustrates how the scheduler
will work. However, each shaded box above does represent a FSM state and will use a clock cycle. Using
the minimum delay values, the ADC can sample at 15 ADC clocks per sample. Below is an example
timing diagram illustrating the states of the sequencer and also the showing when the StepConfig and the
StepDelay registers values are applied. The below example assumes the steps are software controlled,
and averaging is turned off.
1031
SPRUH73H–October 2011–Revised April 2013 Touchscreen Controller
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