1 2 3 4 5 6 7 8 9 10 11
SampleDelay[N]
OpenDelay[N]
Data Valid
13 clock cycles
OpenDelay[N+1]
SampleDelay[N+1]
Apply StepConfig[N]
and StepDelay[N]
Apply StepConfig[N+1]
and StepDelay[N+1]
Idle
Open
SOC
Open
SOC
Apply IdleConfig
Wait for EOC
TimeGen
ADC_CLK
Enable
FSM
SOC
EOC
Data[11:0]
Operational Modes
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Figure 12-4. Example Timing Diagram for Sequencer
The Idle StepConfig is always enabled and applied when the FSM is in the IDLE state (i.e, either waiting
for a HW event or waiting for a step to be enabled). The Idle StepConfig can not be disabled.
Once the TSC_ADC_SS is enabled and assuming at least one StepEnable[N] is active, the FSM will
transition from the Idle state and apply the first active StepConfig[N] and StepDelay[N] register settings. It
is possible for the OpenDelay[N] value to be 0, and therefore the FSM will immediately skip to the
SampleDelay[N] state (which is minimum 1 clock cycle). The ADC will begin the sampling on the falling
edge of the SOC signal. After the ADC is finished converting the channel data (13 cycles later), the EOC
signal is sent and the FSM will then apply the next active step [N+1].
This process is repeated and continued (from step 1 to step 16) until the last active step is completed.
1032
Touchscreen Controller SPRUH73H–October 2011–Revised April 2013
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