Base
Data[3:0]
0123
4 bits/pixel
Bit
Pixel 0
Bit
7
0
Base + 1
Base + 2
Pixel 1
Pixel 2 Pixel 3
Pixel 4 Pixel 5
4 3
Base
Data[7:0]
01234567
8 bits/pixel
Bit
Pixel 0
Pixel 1
Bit
7
0
Base + 1
Pixel 2
Base + 2
Base
BGR
15 01234567891011121314
12 bits/pixel
Bit
Pixel 0
Pixel 1
Bit
15
0
Base + 2
Unused
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Functional Description
Figure 13-9. 12-BPP Data Memory Organization—Little Endian
Unused [15-12] bits are filled with zeroes in TFT mode.
Figure 13-10. 8-BPP Data Memory Organization
Figure 13-11. 4-BPP Data Memory Organization
1113
SPRUH73H–October 2011–Revised April 2013 LCD Controller
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