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Enhanced PWM (ePWM) Module
Table 15-27. EPWMx Initialization for Figure 15-30
Register Bit Value Comments
TBPRD TBPRD 600 (258h) Period = 601 TBCLK counts
TBPHS TBPHS 0 Clear Phase Register to 0
TBCNT TBCNT 0 Clear TB counter
TBCTL CTRMODE TB_UPDOWN
PHSEN TB_DISABLE Phase loading disabled
PRDLD TB_SHADOW
SYNCOSEL TB_SYNC_DISABLE
HSPCLKDIV TB_DIV1 TBCLK = SYSCLK
CLKDIV TB_DIV1
CMPA CMPA 400 (190h) Compare A = 400 TBCLK counts
CMPB CMPB 500 (1F4h) Compare B = 500 TBCLK counts
CMPCTL SHDWAMODE CC_SHADOW
SHDWBMODE CC_SHADOW
LOADAMODE CC_CTR_ZERO Load on CTR = 0
LOADBMODE CC_CTR_ZERO Load on CTR = 0
AQCTLA CAU AQ_SET
CAD AQ_CLEAR
AQCTLB CBU AQ_SET
CBD AQ_CLEAR
Table 15-28. EPWMx Run Time Changes for Figure 15-30
Register Bit Value Comments
CMPA CMPA Duty1A Adjust duty for output EPWM1A
CMPB CMPB Duty1B Adjust duty for output EPWM1B
1529
SPRUH73H–October 2011–Revised April 2013 Pulse-Width Modulation Subsystem (PWMSS)
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