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ARM Cortex-A8 Memory Map
Table 2-1. L3 Memory Map (continued)
Block Name Start_address (hex) End_address (hex) Size Description
Reserved 0x5B00_0000 0x5BFF_FFFF 16MB Reserved
Reserved 0x5C00_0000 0x5DFF_FFFF 32MB Reserved
Reserved 0x5E00_0000 0x5FFF_FFFF 32MB Reserved
Reserved 0x6000_0000 0x7FFF_FFFF 512MB Reserved
EMIF0 SDRAM 0x8000_0000 0xBFFF_FFFF 1GB 8-/16-bit External Memory
(Ex/R/W)
(3)
Reserved 0xC000_0000 0xFFFF_FFFF 1GB Reserved
(3)
Ex/R/W – Execute/Read/Write.
Table 2-2. L4_WKUP Peripheral Memory Map
Region Name Start Address (hex) End Address (hex) Size Description
L4_WKUP configuration 0x44C0_0000 0x44C0_07FF 2KB Address/Protection (AP)
0x44C0_0800 0x44C0_0FFF 2KB Link Agent (LA)
0x44C0_1000 0x44C0_13FF 1KB Initiator Port (IP0)
0x44C0_1400 0x44C0_17FF 1KB Initiator Port (IP1)
Reserved 0x44C0_1800 0x44C0_1FFF 2KB Reserved (IP2 – IP3)
Reserved 0x44C0_2000 0x44CF_FFFF 1MB-8KB Reserved
Reserved 0x44D0_0000 0x44D0_3FFF 16KB Reserved
0x44D0_4000 0x44D0_4FFF 4KB Reserved
Reserved 0x44D0_5000 0x44D7_FFFF 492KB Reserved
Reserved 0x44D8_0000 0x44D8_1FFF 8KB Reserved
0x44D8_2000 0x44D8_2FFF 4KB Reserved
Reserved 0x44D8_3000 0x44DF_FFFF 500KB Reserved
CM_PER 0x44E0_0000 0x44E0_3FFF 1KB Clock Module Peripheral Registers
CM_WKUP 0x44E0_0400 0x44E0_04FF 256 Bytes Clock Module Wakeup Registers
CM_DPLL 0x44E0_0500 0x44E0_05FF 256 Bytes Clock Module PLL Registers
CM_MPU 0x44E0_0600 0x44E0_06FF 256 Bytes Clock Module MPU Registers
CM_DEVICE 0x44E0_0700 0x44E0_07FF 256 Bytes Clock Module Device Registers
CM_RTC 0x44E0_0800 0x44E0_08FF 256 Bytes Clock Module RTC Registers
CM_GFX 0x44E0_0900 0x44E0_09FF 256 Bytes Clock Module Graphics Controller
Registers
CM_CEFUSE 0x44E0_0A00 0x44E0_0AFF 256 Bytes Clock Module Efuse Registers
PRM_IRQ 0x44E0_0B00 0x44E0_0BFF 256 Bytes Power Reset Module Interrupt
Registers
PRM_PER 0x44E0_0C00 0x44E0_0CFF 256 Bytes Power Reset Module Peripheral
Registers
PRM_WKUP 0x44E0_0D00 0x44E0_0DFF 256 Bytes Power Reset Module Wakeup
Registers
PRM_MPU 0x44E0_0E00 0x44E0_0EFF 256 Bytes Power Reset Module MPU
Registers
PRM_DEVICE 0x44E0_0F00 0x44E0_0FFF 256 Bytes Power Reset Module Device
Registers
PRM_RTC 0x44E0_1000 0x44E0_10FF 256 Bytes Power Reset Module RTC
Registers
PRM_GFX 0x44E0_1100 0x44E0_11FF 256 Bytes Power Reset Module Graphics
Controller Registers
PRM_CEFUSE 0x44E0_1200 0x44E0_12FF 256 Bytes Power Reset Module Efuse
Registers
Reserved 0x44E0_3000 0x44E0_3FFF 4KB Reserved
0x44E0_4000 0x44E0_4FFF 4KB Reserved
157
SPRUH73H–October 2011–Revised April 2013 Memory Map
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