I2Async
IceCrusher
MPU_RSTPWRON
SRAM L2
SRAM L1
AXI2OCP
MPU domain
MPU subsystem
ARM Cortex™-A8
Emulation domain
NEON domain
INTC
Core domain
MPU_RST
EMU_RSTPWRON
EMU_RST
NEON_RST
CORE_RST
ARM Cortex-A8 MPU Subsystem
www.ti.com
NOTE: The emulation domain and the core domain are not fully embedded in MPU subsystem.
Figure 3-5. MPU Subsystem Power Domain Overview
Power management requirements at the device level govern power domains for the MPU subsystem. The
device-level power domains are directly aligned with voltage domains and thus can be represented as a
cross reference to the different voltage domains.
Table 3-4 shows the different power domains of the MPU subsystem and the modules inside.
Table 3-4. Overview of the MPU Subsystem Power Domain
Functional Power Domain Physical Power Domain per System/Module
MPU subsystem domain ARM, AXI2OCP, I2Asynch Bridge, ARM L1 and L2 periphery
logic and array, ICE-Crusher, ETM, APB modules
MPU NEON domain ARM NEON accelerator
CORE domain MPU interrupt controller
EMU domain EMU (ETB,DAP)
172
ARM MPU Subsystem SPRUH73H–October 2011–Revised April 2013
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