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GPMC
See Section 7.1.3.9.1 for formulas to calculate timing parameters.
Table 7-41 lists the timing bit fields to set up to configure the GPMC in asynchronous single write mode.
When the GPMC generates a write access to an AAD-multiplexed device, all address bits are driven onto
the address/data bus in two separate phases. The first phase is used for the MSB address and is qualified
with OEn driven low. The second phase for LSB address is qualified with OEn driven high. The address
phase ends at WEn assertion time.
The CSn, WEn, and DIR signals are controlled in the same way as for asynchronous single write
operation on an address/data-multiplexed device.
• Address valid signal ADVn is asserted and deasserted twice during a write transaction
– ADVn first assertion time is controlled by the GPMC_CONFIG3_i[6-4] ADVAADMUXONTIME field.
– ADVn first deassertion time is controlled by the GPMC_CONFIG3_i[30-28]
ADVAADMUXWROFFTIME field.
– ADVn second assertion time is controlled by the GPMC_CONFIG3_i[3-0] ADVONTIME field.
– ADVn second deassertion time is controlled by the GPMC_CONFIG3_i[20-16] ADVWROFFTIME
field.
• Output Enable signal OEn is asserted during the address phase of a write transaction
– OEn assertion time is controlled by the GPMC_CONFIG4_i[6-4] OEAADMUXONTIME field.
– OEn deassertion time is controlled by the GPMC_CONFIG3_i[15-13] OEAADMUXOFFTIME field.
The address bits for the first address phase are driven onto the data bus until OEn deassertion. Data is
driven onto the address/data bus at the clock edge defined by the GPMC_CONFIG6_i[19-16]
WRDATAONADMUXBUS parameter.
7.1.3.3.10.1.2.4 Asynchronous Multiple (Page) Read Operation on an AAD-Multiplexed Device
Write multiple (page) access in asynchronous mode is not supported for AAD-multiplexed devices.
If GPMC_CONFIG1_i[28] WRITEMULTIPLE is enabled (1) with GPMC_CONFIG1_i[27] WRITETYPE as
asynchronous (0), the GPMC processes single asynchronous accesses.
For accesses on non-multiplexed devices, see Section 7.1.3.3.10.3.
7.1.3.3.10.2 Synchronous Access Description
This section details read and write synchronous accesses on address/data multiplexed. All information in
this section can be applied to any type of memory - non-multiplexed, address and data multiplexed or
AAD-multiplexed - with a difference limited to the address phase. For accesses on non-multiplexed
devices, see Section 7.1.3.3.10.3.
In synchronous operations:
• The GPMC_CLK clock is provided outside the GPMC when accessing the memory device.
• The GPMC_CLK clock is derived from the GPMC_FCLK clock using the GPMC_CONFIG1_i[1-0]
GPMCFCLKDIVIDER field. In the following section, i stands for the chip-select number, i = 0 to 3.
• The GPMC_CONFIG1_i[26-25] CLKACTIVATIONTIME field specifies that the GPMC_CLK is provided
outside the GPMC 0, 1, or 2 GPMC_FCLK cycles after start access time until RDCYCLETIME or
WRCYCLETIME completion.
287
SPRUH73H–October 2011–Revised April 2013 Memory Subsystem
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