Texas Instruments AM335 Series

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GPMC_FCLK

GPMC_CLK

WAIT

Valid Address

D 0Valid Address

CSONTIME

ADVONTIME

ADVRDOFFTIME

OEONTIME

OEOFFTIME

CLKACTIVATIONTIME

CSRDOFFTIME

RDACCESSTIME

RDCYCLETIME

nBE1/nBE0

nCS

nADV

nOE

DIR OUT IN OUT

A[27:17]

A[16:1]/D[15:0]

WRDATAONADMUXBUS

GPMC

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7.1.3.3.10.2.1 Synchronous Single Read

Figure 7-17 and Figure 7-18 show a synchronous single-read operation with GPMCFCLKDIVIDER equal

to 0 and 1, respectively.

Figure 7-17. Synchronous Single Read (GPMCFCLKDIVIDER = 0)

288

Memory Subsystem SPRUH73H–October 2011–Revised April 2013

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Table of Contents2
Preface149
1 Introduction150
- 1.1 AM335x Family150
- 1.2 Silicon Revision Functional Differences and Enhancements153
2 Memory Map155
- 2.1 ARM Cortex-A8 Memory Map155
3 ARM MPU Subsystem164
- 3.1 ARM Cortex-A8 MPU Subsystem165
4 Programmable Real-Time Unit and Industrial Communication Subsystem (PRU-ICSS)176
- 4.1 Introduction177
5 Graphics Accelerator (SGX)178
- 5.1 Introduction179
- 5.2 Integration182
- 5.3 Functional Description184
  - 5.3.1 SGX Block Diagram184
  - 5.3.2 SGX Elements Description184
6 Interrupts186
- 6.1 Functional Description187
- 6.2 Basic Programming Model190
- 6.3 ARM Cortex-A8 Interrupts199
- 6.4 PWM Events203
- 6.5 Interrupt Controller Registers204
  - 6.5.1 INTC Registers204
7 Memory Subsystem250
- 7.1 GPMC251
- 7.2 OCMC-RAM398
  - 7.2.1 Introduction398
    - 7.2.1.1 OCMC-RAM Features398
    - 7.2.1.2 Unsupported OCMC-RAM Features398
  - 7.2.2 Integration399
- 7.3 EMIF400
- 7.4 ELM476
8 Power, Reset, and Clock Management (PRCM)499
- 8.1 Power, Reset, and Clock Management500
9 Control Module746
- 9.1 Introduction747
- 9.2 Functional Description747
- 9.3 CONTROL_MODULE Registers757
10 Interconnects863
- 10.1 Introduction864
11 Enhanced Direct Memory Access (EDMA)869
- 11.1 Introduction870
- 11.2 Integration873
  - 11.2.1 Third-Party Channel Controller (TPCC) Integration873
  - 11.2.2 Third-Party Transfer Controller (TPTC) Integration874
- 11.3 Functional Description876
- 11.4 EDMA3 Registers939
  - 11.4.1 EDMA3 Channel Controller Registers939
  - 11.4.2 EDMA3 Transfer Controller Registers993
- 11.5 Appendix A1018
12 Touchscreen Controller1022
- 12.1 Introduction1023
  - 12.1.1 TSC_ADC Features1023
  - 12.1.2 Unsupported TSC_ADC_SS Features1023
- 12.2 Integration1024
- 12.3 Functional Description1026
- 12.4 Operational Modes1029
  - 12.4.1 PenCtrl and PenIRQ1030
- 12.5 Touchscreen Controller Registers1033
  - 12.5.1 TSC_ADC_SS Registers1033
13 LCD Controller1097
- 13.1 Introduction1098
  - 13.1.1 Purpose of the Peripheral1098
  - 13.1.2 Features1099
- 13.2 Integration1100
- 13.3 Functional Description1102
- 13.4 Programming Model1122
- 13.5 LCD Registers1128
14 Ethernet Subsystem1163
- 14.1 Introduction1164
  - 14.1.1 Features1164
  - 14.1.2 Unsupported Features1165
- 14.2 Integration1166
- 14.3 Functional Description1176
- 14.4 Software Operation1235
- 14.5 Ethernet Subsystem Registers1240
15 Pulse-Width Modulation Subsystem (PWMSS)1485
- 15.1 Pulse-Width Modulation Subsystem (PWMSS)1486
- 15.2 Enhanced PWM (ePWM) Module1494
- 15.3 Enhanced Capture (eCAP) Module1607
- 15.4 Enhanced Quadrature Encoder Pulse (eQEP) Module1650
16 Universal Serial Bus (USB)1690
- 16.1 Introduction1691
- 16.2 Integration1694
- 16.3 Functional Description1697
- 16.4 Supported Use Cases1759
- 16.5 USB Registers1760
17 Interprocessor Communication3235
- 17.1 Mailbox3236
- 17.2 Spinlock3306
  - 17.2.1 SPINLOCK Registers3306
18 Multimedia Card (MMC)3344
- 18.1 Introduction3345
  - 18.1.1 MMCHS Features3345
  - 18.1.2 Unsupported MMCHS Features3345
- 18.2 Integration3346
- 18.3 Functional Description3350
- 18.4 Low-Level Programming Models3384
- 18.5 Multimedia Card Registers3389
  - 18.5.1 MULTIMEDIA_CARD Registers3389
19 Universal Asynchronous Receiver/Transmitter (UART)3446
- 19.1 Introduction3447
- 19.2 Integration3449
- 19.3 Functional Description3453
- 19.4 UART/IrDA/CIR Basic Programming Model3496
  - 19.4.1 UART Programming Model3496
    - 19.4.1.1 Quick Start3496
    - 19.4.1.2 Hardware and Software Flow Control Configuration3499
      - 19.4.1.2.1 Hardware Flow Control Configuration3499
      - 19.4.1.2.2 Software Flow Control Configuration3499
  - 19.4.2 IrDA Programming Model3502
- 19.5 UART Registers3505
  - 19.5.1 UART Registers3505
20 Timers3550
- 20.1 DMTimer3551
- 20.2 DMTimer 1ms3585
- 20.3 RTC_SS3621
- 20.4 WATCHDOG3670
21 I2C3698
- 21.1 Introduction3699
  - 21.1.1 I2C Features3699
  - 21.1.2 Unsupported I2C Features3699
- 21.2 Integration3700
- 21.3 Functional Description3702
- 21.4 I2C Registers3716
  - 21.4.1 I2C Registers3716
22 Multichannel Audio Serial Port (McASP)3768
- 22.1 Introduction3769
- 22.2 Integration3771
- 22.3 Functional Description3773
- 22.4 McASP Registers3826
  - 22.4.1 McASP CFG Registers3826
  - 22.4.2 McASP Data Port Registers3880
23 Controller Area Network (CAN)3881
- 23.1 Introduction3882
  - 23.1.1 DCAN Features3882
  - 23.1.2 Unsupported DCAN Features3882
- 23.2 Integration3883
- 23.3 Functional Description3885
- 23.4 DCAN Registers3922
24 Multichannel Serial Port Interface (McSPI)3993
- 24.1 Introduction3994
  - 24.1.1 McSPI Features3994
  - 24.1.2 Unsupported McSPI Features3994
- 24.2 Integration3995
- 24.3 Functional Description3997
- 24.4 McSPI Registers4032
  - 24.4.1 SPI Registers4032
25 General-Purpose Input/Output4056
- 25.1 Introduction4057
- 25.2 Integration4058
- 25.3 Functional Description4061
- 25.4 GPIO Registers4068
  - 25.4.1 GPIO Registers4068
26 Initialization4095
- 26.1 Functional Description4096
27 Debug Subsystem4156
- 27.1 Functional Description4157
  - 27.1.1 Debug Suspend Support for Peripherals4157
    - 27.1.1.1 Debug Subsystem Registers4157
A Revision History4159

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