GPMC
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• Direction signal DIR: DIR goes from OUT to IN at the same time as OEn assertion.
When the GPMC generates a write access to an AAD-multiplexed device, all address bits are driven onto
the address/data bus in two separate phases. The first phase is used for the MSB address and is qualified
with OEn driven low. The second phase for LSB address is qualified with OEn driven high. The address
phase ends at WEn assertion time.
The CSn and DIR signals are controlled in the same way as for synchronous single read operation on an
address/data-multiplexed device.
• Address valid signal ADVn is asserted and deasserted twice during a read transaction
– ADVn first assertion time is controlled by the GPMC_CONFIG3_i[6-4] ADVAADMUXONTIME field.
– ADVn first deassertion time is controlled by the GPMC_CONFIG3_i[26-24]
ADVAADMUXRDOFFTIME field.
– ADVn second assertion time is controlled by the GPMC_CONFIG3_i[3-0] ADVONTIME field.
– ADVn second deassertion time is controlled by the GPMC_CONFIG3_i[12-8] ADVRDOFFTIME
field.
• Output Enable signal OEn is asserted and deasserted twice during a read transaction (OEn second
assertion indicates a read cycle)
– OEn first assertion time is controlled by the GPMC_CONFIG4_i[6-4] OEAADMUXONTIME field.
– OEn first deassertion time is controlled by the GPMC_CONFIG3_i[15-13] OEAADMUXOFFTIME
field.
– OEn second assertion time is controlled by the GPMC_CONFIG4_i[3-0] OEONTIME field.
– OEn second deassertion time is controlled by the GPMC_CONFIG4_i[12-8] OEOFFTIME field.
After a read operation, if no other access (read or write) is pending, the data bus is driven with the
previous read value. See Section 7.1.3.3.9.10.
290
Memory Subsystem SPRUH73H–October 2011–Revised April 2013
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