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13-29. RASTER_TIMING_0 Register ........................................................................................ 1141
13-30. RASTER_TIMING_1 Register ........................................................................................ 1142
13-31. RASTER_TIMING_2 Register ........................................................................................ 1143
13-32. RASTER_SUBPANEL Register ...................................................................................... 1145
13-33. RASTER_SUBPANEL2 Register..................................................................................... 1146
13-34. LCDDMA_CTRL Register ............................................................................................. 1147
13-35. LCDDMA_FB0_BASE Register....................................................................................... 1148
13-36. LCDDMA_FB0_CEILING Register ................................................................................... 1149
13-37. LCDDMA_FB1_BASE Register....................................................................................... 1150
13-38. LCDDMA_FB1_CEILING Register ................................................................................... 1151
13-39. SYSCONFIG Register ................................................................................................. 1152
13-40. IRQSTATUS_RAW Register.......................................................................................... 1153
13-41. IRQSTATUS Register.................................................................................................. 1155
13-42. IRQENABLE_SET Register........................................................................................... 1157
13-43. IRQENABLE_CLEAR Register ....................................................................................... 1159
13-44. CLKC_ENABLE Register.............................................................................................. 1161
13-45. CLKC_RESET Register ............................................................................................... 1162
14-1. Ethernet Switch Integration ........................................................................................... 1166
14-2. Ethernet Switch RMII Clock Detail ................................................................................... 1170
14-3. MII Interface Connections ............................................................................................. 1171
14-4. RMII Interface Connections ........................................................................................... 1173
14-5. RGMII Interface Connections ......................................................................................... 1174
14-6. CPSW_3G Block Diagram ............................................................................................ 1182
14-7. Tx Buffer Descriptor Format .......................................................................................... 1187
14-8. Rx Buffer Descriptor Format .......................................................................................... 1190
14-9. VLAN Header Encapsulation Word .................................................................................. 1194
14-10. CPTS Block Diagram .................................................................................................. 1228
14-11. Event FIFO Misalignment Condition ................................................................................. 1230
14-12. HW1/4_TSP_PUSH Connection...................................................................................... 1231
14-13. Port TX State RAM Entry.............................................................................................. 1236
14-14. Port RX DMA State..................................................................................................... 1237
14-15. IDVER Register......................................................................................................... 1241
14-16. CONTROL Register.................................................................................................... 1242
14-17. PRESCALE Register................................................................................................... 1244
14-18. UNKNOWN_VLAN Register .......................................................................................... 1245
14-19. TBLCTL Register ....................................................................................................... 1246
14-20. TBLW2 Register ........................................................................................................ 1247
14-21. TBLW1 Register ........................................................................................................ 1248
14-22. TBLW0 Register ........................................................................................................ 1249
14-23. PORTCTL0 Register ................................................................................................... 1250
14-24. PORTCTL1 Register ................................................................................................... 1251
14-25. PORTCTL2 Register ................................................................................................... 1252
14-26. PORTCTL3 Register ................................................................................................... 1253
14-27. PORTCTL4 Register ................................................................................................... 1254
14-28. PORTCTL5 Register ................................................................................................... 1255
14-29. TX_IDVER Register.................................................................................................... 1258
14-30. TX_CONTROL Register ............................................................................................... 1259
14-31. TX_TEARDOWN Register ............................................................................................ 1260
14-32. RX_IDVER Register.................................................................................................... 1261
31
SPRUH73H–October 2011–Revised April 2013 List of Figures
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